[Intel-gfx] [PATCH 03/15] drm/i915: Split execlists/guc reset prepartions
chris at chris-wilson.co.uk
Wed Mar 28 21:18:45 UTC 2018
In the next patch, we will make the execlists reset prepare callback
take into account preemption by flushing the context-switch handler.
This is not applicable to the GuC submission backend, so split the two
into their own backend callbacks.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski at intel.com>
CC: Michel Thierry <michel.thierry at intel.com>
Cc: Jeff McGee <jeff.mcgee at intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee at intel.com>
drivers/gpu/drm/i915/intel_guc_submission.c | 41 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_lrc.c | 11 +-------
2 files changed, 42 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 207cda062626..2d0f1a04efea 100644
@@ -776,6 +776,46 @@ static void guc_submission_tasklet(unsigned long data)
+static struct i915_request *
+guc_reset_prepare(struct intel_engine_cs *engine)
+ struct intel_engine_execlists * const execlists = &engine->execlists;
+ GEM_TRACE("%s\n", engine->name);
+ * Prevent request submission to the hardware until we have
+ * completed the reset in i915_gem_reset_finish(). If a request
+ * is completed by one engine, it may then queue a request
+ * to a second via its execlists->tasklet *just* as we are
+ * calling engine->init_hw() and also writing the ELSP.
+ * Turning off the execlists->tasklet until the reset is over
+ * prevents the race.
+ * Note that this needs to be a single atomic operation on the
+ * tasklet (flush existing tasks, prevent new tasks) to prevent
+ * a race between reset and set-wedged. It is not, so we do the best
+ * we can atm and make sure we don't lock the machine up in the more
+ * common case of recursively being called from set-wedged from inside
+ * i915_reset.
+ if (!atomic_read(&execlists->tasklet.count))
+ * We're using worker to queue preemption requests from the tasklet in
+ * GuC submission mode.
+ * Even though tasklet was disabled, we may still have a worker queued.
+ * Let's make sure that all workers scheduled before disabling the
+ * tasklet are completed before continuing with the reset.
+ if (engine->i915->guc.preempt_wq)
+ return i915_gem_find_active_request(engine);
* Everything below here is concerned with setup & teardown, and is
* therefore not part of the somewhat time-critical batch-submission
@@ -1235,6 +1275,7 @@ int intel_guc_submission_enable(struct intel_guc *guc)
execlists->tasklet.func = guc_submission_tasklet;
+ engine->reset.prepare = guc_reset_prepare;
engine->park = guc_submission_park;
engine->unpark = guc_submission_unpark;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 89ed9e236b0e..540e437d9783 100644
@@ -1736,16 +1736,6 @@ execlists_reset_prepare(struct intel_engine_cs *engine)
- * We're using worker to queue preemption requests from the tasklet in
- * GuC submission mode.
- * Even though tasklet was disabled, we may still have a worker queued.
- * Let's make sure that all workers scheduled before disabling the
- * tasklet are completed before continuing with the reset.
- if (engine->i915->guc.preempt_wq)
@@ -2135,6 +2125,7 @@ static void execlists_set_default_submission(struct intel_engine_cs *engine)
engine->cancel_requests = execlists_cancel_requests;
engine->schedule = execlists_schedule;
engine->execlists.tasklet.func = execlists_submission_tasklet;
+ engine->reset.prepare = execlists_reset_prepare;
engine->park = NULL;
engine->unpark = NULL;
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