[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
URL   : https://patchwork.freedesktop.org/series/40839/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9ae66e05586d drm: Add DP PSR2 sink enable bit
ea5ff834dac7 drm: Add DP last received PSR SDP VSC register and bits
c4ff90984726 drm/i915/psr: Nuke aux frame sync
45b2682dc7e8 drm/i915/psr: Tie PSR2 support to Y coordinate requirement
4cc799de37d9 drm/i915/psr/cnl: Enable Y-coordinate support in source
-:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:4061:
+#define   EDP_Y_COORDINATE_VALID	(1<<26) /* GLK and CNL+ */
                                 	  ^

-:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:4062:
+#define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
                                  	  ^

-:35: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:7069:
+#define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1<<25) /* GLK and CNL+ */
                                       	  ^

total: 0 errors, 0 warnings, 3 checks, 43 lines checked
5c9248d38cda drm/i915/psr: Do not override PSR2 sink support
bf021489296c drm/i915/psr: Use PSR2 macro for PSR2
82122405ae92 drm/i915/psr: Cache sink synchronization latency
20e02342f2b0 drm/i915/psr: Set DPCD PSR2 enable bit when needed
2ec83428a832 drm/i915/debugfs: Print sink PSR status