[Intel-gfx] [PATCH v7 11/23] drm/i915/icl: Configure DSI transcoders

[Madhav Chauhan]

On 10/15/2018 7:57 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan at intel.com>
>
> This patch programs DSI operation mode, pixel format,
> BGR info, link calibration etc for the DSI transcoder.
> This patch also extract BGR info of the DSI panel from
> VBT and save it inside struct intel_dsi which used for
> configuring DSI transcoder.
>
> v2: Rebase
> v3: Use newly defined bitfields.
>
> v4 by Jani:
>   - Use intel_dsi_bitrate()
>   - Make bgr_enabled bool
>   - Use 0 instead of 0x0
>   - Replace DRM_ERROR() with MISSING_CASE() on pixel format and video mode
>   - Use is_vid_mode()

v4 changes are fine.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan at intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c       | 87 +++++++++++++++++++++++++++++++++++-
>   drivers/gpu/drm/i915/intel_dsi.h     |  3 ++
>   drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
>   3 files changed, 90 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 407c3065d08d..756c75d0c86c 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -27,7 +27,7 @@
>   
>   #include "intel_dsi.h"
>   
> -static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(enum port port)
> +static enum transcoder dsi_port_to_transcoder(enum port port)
>   {
>   	if (port == PORT_A)
>   		return TRANSCODER_DSI_0;
> @@ -340,6 +340,88 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>   	}
>   }
>   
> +static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u32 tmp;
> +	enum port port;
> +	enum transcoder dsi_trans;
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +		tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
> +
> +		if (intel_dsi->eotp_pkt)
> +			tmp &= ~EOTP_DISABLED;
> +		else
> +			tmp |= EOTP_DISABLED;
> +
> +		/* enable link calibration if freq > 1.5Gbps */
> +		if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
> +			tmp &= ~LINK_CALIBRATION_MASK;
> +			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
> +		}
> +
> +		/* configure continuous clock */
> +		tmp &= ~CONTINUOUS_CLK_MASK;
> +		if (intel_dsi->clock_stop)
> +			tmp |= CLK_ENTER_LP_AFTER_DATA;
> +		else
> +			tmp |= CLK_HS_CONTINUOUS;
> +
> +		/* configure buffer threshold limit to minimum */
> +		tmp &= ~PIX_BUF_THRESHOLD_MASK;
> +		tmp |= PIX_BUF_THRESHOLD_1_4;
> +
> +		/* set virtual channel to '0' */
> +		tmp &= ~PIX_VIRT_CHAN_MASK;
> +		tmp |= PIX_VIRT_CHAN(0);
> +
> +		/* program BGR transmission */
> +		if (intel_dsi->bgr_enabled)
> +			tmp |= BGR_TRANSMISSION;
> +
> +		/* select pixel format */
> +		tmp &= ~PIX_FMT_MASK;
> +		switch (intel_dsi->pixel_format) {
> +		default:
> +			MISSING_CASE(intel_dsi->pixel_format);
> +			/* fallthrough */
> +		case MIPI_DSI_FMT_RGB565:
> +			tmp |= PIX_FMT_RGB565;
> +			break;
> +		case MIPI_DSI_FMT_RGB666_PACKED:
> +			tmp |= PIX_FMT_RGB666_PACKED;
> +			break;
> +		case MIPI_DSI_FMT_RGB666:
> +			tmp |= PIX_FMT_RGB666_LOOSE;
> +			break;
> +		case MIPI_DSI_FMT_RGB888:
> +			tmp |= PIX_FMT_RGB888;
> +			break;
> +		}
> +
> +		/* program DSI operation mode */
> +		if (is_vid_mode(intel_dsi)) {
> +			tmp &= ~OP_MODE_MASK;
> +			switch (intel_dsi->video_mode_format) {
> +			default:
> +				MISSING_CASE(intel_dsi->video_mode_format);
> +				/* fallthrough */
> +			case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
> +				tmp |= VIDEO_MODE_SYNC_EVENT;
> +				break;
> +			case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
> +				tmp |= VIDEO_MODE_SYNC_PULSE;
> +				break;
> +			}
> +		}
> +
> +		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
> +	}
> +}
> +
>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>   {
>   	/* step 4a: power up all lanes of the DDI used by DSI */
> @@ -356,6 +438,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>   
>   	/* setup D-PHY timings */
>   	gen11_dsi_setup_dphy_timings(encoder);
> +
> +	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
> +	gen11_dsi_configure_transcoder(encoder);
>   }
>   
>   static void __attribute__((unused))
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 12b758ebefce..14567929de9a 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -81,6 +81,9 @@ struct intel_dsi {
>   	u16 dcs_backlight_ports;
>   	u16 dcs_cabc_ports;
>   
> +	/* RGB or BGR */
> +	bool bgr_enabled;
> +
>   	u8 pixel_overlap;
>   	u32 port_bits;
>   	u32 bw_timer;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 3035422aa0d6..cca071406c25 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -805,6 +805,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>   	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
>   	intel_dsi->video_frmt_cfg_bits =
>   		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
> +	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
>   
>   	/* Starting point, adjusted depending on dual link and burst mode */
>   	intel_dsi->pclk = mode->clock;