[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev6)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev6)
URL   : https://patchwork.freedesktop.org/series/44823/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
33aac050cb0a drm/i915/icl: Configure lane sequencing of combo phy transmitter
-:59: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#59: FILE: drivers/gpu/drm/i915/icl_dsi.c:142:
+
+}

total: 0 errors, 0 warnings, 1 checks, 49 lines checked
ef7b1857842d drm/i915/icl: DSI vswing programming sequence
-:35: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#35: FILE: drivers/gpu/drm/i915/icl_dsi.c:39:
+	for_each_dsi_port(port, intel_dsi->ports) {
+

total: 0 errors, 0 warnings, 1 checks, 138 lines checked
95defd9d09d2 drm/i915/icl: Enable DDI Buffer
70390672d720 drm/i915/icl: Program T_INIT_MASTER registers
c6b328ee922e drm/i915/icl: Define data/clock lanes dphy timing registers
4f586b27f1d8 drm/i915/icl: Program DSI clock and data lane timing params
-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:631:
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+				mipi_config->tclk_prepare);

-:116: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#116: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:655:
+		clk_zero_cnt = DIV_ROUND_UP(

-:130: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#130: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:669:
+		hs_zero_cnt = DIV_ROUND_UP(

-:192: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#192: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:727:
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
+							ui_num * mul);

-:198: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#198: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:731:
+			DRM_DEBUG_KMS("prepare count too high %u\n",
+								prepare_cnt);

-:203: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#203: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:736:
+		exit_zero_cnt = DIV_ROUND_UP(

-:228: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#228: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:748:
+		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
+					(55 * ui_den) % ui_num)

-:233: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#233: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:753:
+			DRM_DEBUG_KMS("exit zero count too high %u\n",
+								exit_zero_cnt);

-:252: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#252: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:764:
+			DRM_DEBUG_KMS("clock zero count too high %u\n",
+								clk_zero_cnt);

total: 0 errors, 0 warnings, 9 checks, 293 lines checked
00e8d4a4da2e drm/i915/icl: Define TA_TIMING_PARAM registers
9633b65f73df drm/i915/icl: Program TA_TIMING_PARAM registers
330b8eaf31ad drm/i915/icl: Get DSI transcoder for a given port
-:20: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#20: FILE: drivers/gpu/drm/i915/icl_dsi.c:30:
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(

total: 0 errors, 0 warnings, 1 checks, 27 lines checked
25067852a150 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
2ba056a34af8 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
-:47: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#47: FILE: drivers/gpu/drm/i915/i915_reg.h:10396:
+#define  PIX_VIRT_CHAN(x)		(x << 12)

total: 0 errors, 0 warnings, 1 checks, 54 lines checked
74707887f37e drm/i915/icl: Configure DSI transcoders
9bdf8144d433 drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
d41c7f8dd938 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
-:21: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#21: FILE: drivers/gpu/drm/i915/icl_dsi.c:344:
+static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
+				const struct intel_crtc_state *pipe_config)

-:87: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#87: FILE: drivers/gpu/drm/i915/icl_dsi.c:476:
+static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
+				const struct intel_crtc_state *pipe_config)

total: 0 errors, 0 warnings, 2 checks, 88 lines checked
605fd9be0d02 drm/i915/icl: Define DSI transcoder timing registers
f3f7796930bb drm/i915/icl: Configure DSI transcoder timings
-:24: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#24: FILE: drivers/gpu/drm/i915/icl_dsi.c:476:
+static void gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
+				const struct intel_crtc_state *pipe_config)

-:52: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#52: FILE: drivers/gpu/drm/i915/icl_dsi.c:504:
+	vsync_shift = hsync_start - htotal/2;
 	                                  ^

-:66: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666'
#66: FILE: drivers/gpu/drm/i915/icl_dsi.c:518:
+	if ((intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666) &&
+	    ((hactive % 4) != 0))

total: 0 errors, 0 warnings, 3 checks, 138 lines checked
574f03ac11ac drm/i915/icl: Define TRANS_CONF register for DSI
21de99317a80 drm/i915/icl: Enable DSI transcoders
2cbb64e9d49c drm/i915/icl: Define DSI panel programming registers
78802bf69fe2 drm/i915/icl: Set max return packet size for DSI panel