[Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
Anuj Phogat
anuj.phogat at gmail.com
Fri Apr 26 17:01:37 UTC 2019
On Thu, Apr 18, 2019 at 3:06 AM Tvrtko Ursulin
<tvrtko.ursulin at linux.intel.com> wrote:
>
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>
> WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
> to benefit 3d workloads but media has different requirements.
>
> Remove the workaround and whitelist the register to allow any userspace
> configure the behaviour to their liking.
>
> v2:
> * Remove the workaround apart from adding the whitelist.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> Cc: kevin.ma at intel.com
> Cc: xiaogang.li at intel.com
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index b3cbed1ee1c9..baed186724d2 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -556,10 +556,6 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
>
> - /* WaEnableStateCacheRedirectToCS:icl */
> - WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
> - GEN11_STATE_CACHE_REDIRECT_TO_CS);
> -
> /* Wa_2006665173:icl (pre-prod) */
> if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
> WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> @@ -1070,6 +1066,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
>
> /* WaAllowUMDToModifySamplerMode:icl */
> whitelist_reg(w, GEN10_SAMPLER_MODE);
> +
> + /* WaEnableStateCacheRedirectToCS:icl */
> + whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
> }
>
> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> --
> 2.19.1
>
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Acked-by: Anuj Phogat <anuj.phogat at gmail.com>
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