[Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1

[Li, Xiaogang]

So we can check in this patch right now, right?

-----Original Message-----
From: Anuj Phogat [mailto:anuj.phogat at gmail.com] 
Sent: Tuesday, April 30, 2019 1:17 AM
To: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>
Cc: Phogat, Anuj <anuj.phogat at intel.com>; Joonas Lahtinen <joonas.lahtinen at linux.intel.com>; Intel GFX <Intel-gfx at lists.freedesktop.org>; Landwerlin, Lionel G <lionel.g.landwerlin at intel.com>; Ma, Kevin <kevin.ma at intel.com>; Li, Xiaogang <xiaogang.li at intel.com>
Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1

On Sun, Apr 28, 2019 at 10:57 PM Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> wrote:
>
>
> On 26/04/2019 17:58, Anuj Phogat wrote:
> >
> > Joonas,
> >
> > Mesa now applies this WA on ICL and we're not seeing any regressions in CI.
> > I tested Mesa with and without this patch applied to kernel. I don't 
> > see any performance impact to Manhattan from GfxBench5. I'm little 
> > surprised to see it's not really helping benchmark performance in 
> > Mesa. I'll dig bit more to figure out a possible explanation. I 
> > haven't tried any other benchmarks with this patch.
>
> I think the concern was, if user is running old Mesa (no WA) on new 
> kernel (no WA) there wouldn't be any GPU hangs, just theoretical (yet
> unmeasured) perf drop?
>
I also tested Manhattan with Mesa (no WA) and Kernel (no WA) and didn't see a GPU hang or any perf drop. The no change in perf might be due to currently used L3 configuration in Mesa which doesn't allocate anything to  CS Command buffer section. Mesa now carries the WA in case we choose to use a different L3 config in future.

> Regards,
>
> Tvrtko
>
> >
> > Thanks
> > Anuj
> > On 04/26/2019 01:31 AM, Joonas Lahtinen wrote:
> >> + Anuj
> >>
> >> Quoting Lionel Landwerlin (2019-04-26 11:13:58)
> >>> On 18/04/2019 18:06, Tvrtko Ursulin wrote:
> >>>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> >>>>
> >>>> WaEnableStateCacheRedirectToCS context workaround configures the 
> >>>> L3 cache to benefit 3d workloads but media has different 
> >>>> requirements.
> >>>>
> >>>> Remove the workaround and whitelist the register to allow any 
> >>>> userspace configure the behaviour to their liking.
> >>>>
> >>>> v2:
> >>>>    * Remove the workaround apart from adding the whitelist.
> >>>>
> >>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> >>>> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> >>>> Cc: kevin.ma at intel.com
> >>>> Cc: xiaogang.li at intel.com
> >>>
> >>> Acked-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> >>>
> >>>
> >>> Mesa commits :
> >>>
> >>> commit db5b372bb9f5a0dfea86618f8f9832f25d9eaf71 (anv)
> >>>
> >>> commit eaadb62c9ea98f841d7ffc26c14341abdf84d2d6 (i965)
> >>>
> >>> commit d1be67db39463b48369cb71979ed18662b2c157e (iris)
> >> Could somebody confirm that applying this patch does not cause 
> >> hangs in older mesa, and the performance drop (if any) is insignificant?
> >>
> >> Best Regards,
> >> Joonas
> >
> >
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx