[Intel-gfx] [PATCH] drm/i915/icl: Remove DDI IO power domain from PG3 power domains

Imre Deak imre.deak at intel.com
Mon Aug 5 10:05:56 UTC 2019


On Mon, Aug 05, 2019 at 12:49:13PM +0300, Imre Deak wrote:
> On Wed, Jul 31, 2019 at 09:03:24AM +0530, Anshuman Gupta wrote:
> 
> > DDI IO power domain are in IO/PHY/AFE power domains.  Which does not
> > require PG3 power well to be enable.
> 
> Thanks for tracking this down.
> 
> Imo the commit message would be clearer by saying:
> 
> The DDI-IO power wells are backing the IO/PHY functionality which
> doesn't need the PG3 power power well. Accordingly fix up the list of
> PG3 power domains.
> 
> > MIPI DSI dual link gets "DDI B" IO power domain reference count which
> > enables PG3 since "DDI B" IO power domain is part of PG3 power domain,
> > that makes power leakage in MIPI DSI dual link use case.
> 
> > 
> > Cc: Deak Imre <imre.deak at intel.com>
> > Cc: Syrjala Ville <ville.syrjala at intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_power.c | 3 ---
> >  1 file changed, 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index dd2a50b8ba0a..ca33e8d41218 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -2482,11 +2482,8 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> >  	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> >  	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
> >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |	\
> > -	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |		\
> >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |	\
> > -	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |		\
> >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |	\
> > -	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |		\
> >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |	\
> >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |		\
> 
> What about the E/F ports' IO power wells?

Also TGL_PW_3_POWER_DOMAINS needs to be fixed the same way.

> 
> >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |	\
> > -- 
> > 2.21.0
> > 
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