[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Tiger Lake batch 3

[Patchwork]

== Series Details ==

Series: Tiger Lake batch 3
URL   : https://patchwork.freedesktop.org/series/65290/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: do not use DDIC
Okay!

Commit: drm/i915/psr: Make PSR registers relative to transcoders
Okay!

Commit: drm/i915: Add transcoder restriction to PSR2
Okay!

Commit: drm/i915: Do not unmask PSR interruption in IRQ postinstall
Okay!

Commit: drm/i915/psr: Only handle interruptions of the transcoder in use
Okay!

Commit: drm/i915/bdw+: Enable PSR in any eDP port
Okay!

Commit: drm/i915: Guard and warn if more than one eDP panel is present
Okay!

Commit: drm/i915/tgl: Change PSR2 transcoder restriction
Okay!

Commit: drm/i915: Do not read PSR2 register in transcoders without PSR2
Okay!

Commit: drm/i915/tgl: PSR link standby is not supported anymore
Okay!

Commit: drm/i915/tgl: Access the right register when handling PSR interruptions
Okay!

Commit: drm/i915/tgl: Add maximum resolution supported by PSR2 HW
Okay!

Commit: drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
Okay!

Commit: drm/i915: Add for_each_new_intel_connector_in_state()
Okay!

Commit: drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
Okay!

Commit: drm/i915: Disable pipes in reverse order
Okay!

Commit: drm/i915/tgl: Select master transcoder in DP MST
Okay!

Commit: drm/i915/tgl: Introduce initial Tiger Lake workarounds
Okay!

Commit: drm/i915/tgl: Implement Wa_1406941453
Okay!

Commit: drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
Okay!

Commit: drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
Okay!

Commit: drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
Okay!

Commit: drm/i915/tgl: Register state context definition for Gen12
Okay!

Commit: drm/i915/tgl: move DP_TP_* to transcoder
Okay!

Commit: drm/i915/tgl: Implement TGL DisplayPort training sequence
Okay!

Commit: HACK: drm/i915/tgl: Gen12 render context size
Okay!

Commit: drm/i915/tgl: add Gen12 default indirect ctx offset
Okay!

Commit: drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
Okay!

Commit: drm/i915/tgl: Report valid VDBoxes with SFC capability
Okay!

Commit: drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
Okay!

Commit: drm/i915/tgl: Updated Private PAT programming
Okay!

Commit: drm/i915/tgl/perf: use the same oa ctx_id format as icl
Okay!

Commit: drm/i915/perf: add a parameter to control the size of OA buffer
-O:drivers/gpu/drm/i915/i915_perf.c:1436:15: warning: memset with byte count of 16777216
-O:drivers/gpu/drm/i915/i915_perf.c:1495:15: warning: memset with byte count of 16777216

Commit: drm/i915/tgl: Add perf support on TGL
Okay!

Commit: drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
Okay!