[Intel-gfx] [PATCH v2 15/15] drm/i915/dsb: Enable gamma lut programming using DSB.

[Animesh Manna]

On 8/22/2019 6:53 PM, Jani Nikula wrote:
> On Wed, 21 Aug 2019, Animesh Manna <animesh.manna at intel.com> wrote:
>> Gamma lut programming can be programmed using DSB
>> where bulk register programming can be done using indexed
>> register write which takes number of data and the mmio offset
>> to be written.
> No. Please stick to adding and using the relevant intel dsb write
> routines for switching areas to using DSB.

Thanks for review Jani, will reroll a new version soon.

Regards,
Animesh
>
> BR,
> Jani.
>
>> Cc: Jani Nikula <jani.nikula at intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna at intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_color.c |  4 ++++
>>   drivers/gpu/drm/i915/i915_reg.h            | 25 +++++++++++++++-------
>>   2 files changed, 21 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>> index 71a0201437a9..866e9306f4c9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>> @@ -882,6 +882,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>>   {
>>   	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
>>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>   
>>   	if (crtc_state->base.degamma_lut)
>>   		glk_load_degamma_lut(crtc_state);
>> @@ -900,6 +901,8 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>>   		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
>>   		ivb_load_lut_ext_max(crtc);
>>   	}
>> +
>> +	intel_dsb_commit(dev_priv->dsb);
>>   }
>>   
>>   static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
>> @@ -980,6 +983,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
>>   {
>>   	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>>   
>> +	dev_priv->dsb = crtc_state->dsb;
> Cringe.
>
>>   	dev_priv->display.load_luts(crtc_state);
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index a1a9d09b6420..4d70ae6a6a2d 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -242,7 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>>   #define _PORT(port, a, b)		_PICK_EVEN(port, a, b)
>>   #define _PLL(pll, a, b)			_PICK_EVEN(pll, a, b)
>>   
>> -#define _MMIO_PIPE(pipe, a, b)		_MMIO(_PIPE(pipe, a, b))
>> +#define _MMIO_PIPE(pipe, a, b, ...)	_MMIO(_PIPE(pipe, a, b), ##__VA_ARGS__)
>>   #define _MMIO_PLANE(plane, a, b)	_MMIO(_PLANE(plane, a, b))
>>   #define _MMIO_TRANS(tran, a, b)		_MMIO(_TRANS(tran, a, b))
>>   #define _MMIO_PORT(port, a, b)		_MMIO(_PORT(port, a, b))
>> @@ -10246,11 +10246,18 @@ enum skl_power_gate {
>>   #define _PAL_PREC_EXT2_GC_MAX_B	0x4AC30
>>   #define _PAL_PREC_EXT2_GC_MAX_C	0x4B430
>>   
>> -#define PREC_PAL_INDEX(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
>> -#define PREC_PAL_DATA(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
>> -#define PREC_PAL_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
>> -#define PREC_PAL_EXT_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
>> -#define PREC_PAL_EXT2_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
>> +#define PREC_PAL_INDEX(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, \
>> +						   _PAL_PREC_INDEX_B, \
>> +						   DSB_WRITE)
>> +#define PREC_PAL_DATA(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_DATA_A, \
>> +						   _PAL_PREC_DATA_B, \
>> +						   DSB_INDEX_WRITE)
>> +#define PREC_PAL_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4, \
>> +					      DSB_WRITE)
>> +#define PREC_PAL_EXT_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4, \
>> +					      DSB_WRITE)
>> +#define PREC_PAL_EXT2_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4, \
>> +					      DSB_WRITE)
>>   
>>   #define _PRE_CSC_GAMC_INDEX_A	0x4A484
>>   #define _PRE_CSC_GAMC_INDEX_B	0x4AC84
>> @@ -10274,10 +10281,12 @@ enum skl_power_gate {
>>   
>>   #define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
>>   					_PAL_PREC_MULTI_SEG_INDEX_A, \
>> -					_PAL_PREC_MULTI_SEG_INDEX_B)
>> +					_PAL_PREC_MULTI_SEG_INDEX_B, \
>> +					DSB_WRITE)
>>   #define PREC_PAL_MULTI_SEG_DATA(pipe)	_MMIO_PIPE(pipe, \
>>   					_PAL_PREC_MULTI_SEG_DATA_A, \
>> -					_PAL_PREC_MULTI_SEG_DATA_B)
>> +					_PAL_PREC_MULTI_SEG_DATA_B, \
>> +					DSB_INDEX_WRITE)
>>   
>>   /* pipe CSC & degamma/gamma LUTs on CHV */
>>   #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)