[Intel-gfx] [PATCH] drm/i915/psr: Bump vblank evasion time for seamless updates

[Chris Wilson]

Quoting Ville Syrjälä (2019-02-13 16:30:10)
> On Wed, Feb 13, 2019 at 04:21:42PM +0000, Chris Wilson wrote:
> > Each set of registers we need to rewrite during a pageflip/modeset
> > increases the required evasion window. Modesets with PSR enabled
> > empirically take up to 350us to complete the register programming, so
> > provide a corresponding boost to the evasion window.
> 
> We should have exited PSR before the evasion. Is that code not working?

I'm just correlating the reports that with PSR we get more missed vblank
evasion warnings; iirc CI showed the same when it was force enabled.

It was a neat theory to start explaining how to decide how high an
evasion time we require.
-Chris