[Intel-gfx] [PATCH v2 25/25] drm/i915/tgl: Update DPLL clock reference register

[Ville Syrjälä]

On Mon, Jul 08, 2019 at 04:16:29PM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza at intel.com>
> 
> This register definition changed from ICL and has now another meaning.
> Use the right bits on TGL.
> 
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++++--
>  drivers/gpu/drm/i915/i915_reg.h               | 1 +
>  2 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 330b42a1f54e..9793039485e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2597,8 +2597,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
>  	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
>  		 DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
>  		 DPLL_CFGCR1_KDIV(pll_params.kdiv) |
> -		 DPLL_CFGCR1_PDIV(pll_params.pdiv) |
> -		 DPLL_CFGCR1_CENTRAL_FREQ_8400;
> +		 DPLL_CFGCR1_PDIV(pll_params.pdiv);
> +
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
> +	else
> +		cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
>  
>  	memset(pll_state, 0, sizeof(*pll_state));
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84c04ea67ec8..a244e8158aee 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9947,6 +9947,7 @@ enum skl_power_gate {
>  #define  DPLL_CFGCR1_PDIV_7		(8 << 2)
>  #define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
>  #define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
> +#define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)

I'd probably leave this out entirely if we're not going to define the
other values of thess bits.

Either way
Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

>  #define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
>  
>  #define _ICL_DPLL0_CFGCR0		0x164000
> -- 
> 2.21.0

-- 
Ville Syrjälä
Intel