[Intel-gfx] [PATCH v8 06/13] drm/i915/perf: implement active wait for noa configurations

[Chris Wilson]

Quoting Umesh Nerlige Ramappa (2019-07-11 00:43:21)
> On Tue, Jul 09, 2019 at 03:33:44PM +0300, Lionel Landwerlin wrote:
> >+static u32 *save_register(struct drm_i915_private *i915, u32 *cs,
> >+                        i915_reg_t reg, u32 offset, u32 dword_count)
> >+{
> >+      uint32_t d;
> >+
> >+      for (d = 0; d < dword_count; d++) {
> >+              *cs++ = INTEL_GEN(i915) >= 8 ?
> >+                      MI_STORE_REGISTER_MEM_GEN8 : MI_STORE_REGISTER_MEM;
> >+              *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
> >+              *cs++ = intel_gt_scratch_offset(&i915->gt, offset) + 4 * d;
> >+              *cs++ = 0;
> >+      }
> >+
> >+      return cs;
> >+}
> >+
> >+static u32 *restore_register(struct drm_i915_private *i915, u32 *cs,
> >+                           i915_reg_t reg, u32 offset, u32 dword_count)
> >+{
> >+      uint32_t d;
> >+
> >+      for (d = 0; d < dword_count; d++) {
> >+              *cs++ = INTEL_GEN(i915) >= 8 ?
> >+                      MI_LOAD_REGISTER_MEM_GEN8 : MI_LOAD_REGISTER_MEM;
> >+              *cs++ = i915_mmio_reg_offset(reg);
> >+              *cs++ = intel_gt_scratch_offset(&i915->gt, offset);
> 
> are you missing + 4 * d in the above 2 lines?

Whoops bad reviewer. Since these are the same two loops just with a
different cmd...
-Chris