[Intel-gfx] [PATCH v8 06/13] drm/i915/perf: implement active wait for noa configurations
Lionel Landwerlin
lionel.g.landwerlin at intel.com
Thu Jul 11 07:47:19 UTC 2019
On 11/07/2019 09:29, Chris Wilson wrote:
> Quoting Umesh Nerlige Ramappa (2019-07-11 00:43:21)
>> On Tue, Jul 09, 2019 at 03:33:44PM +0300, Lionel Landwerlin wrote:
>>> +static u32 *save_register(struct drm_i915_private *i915, u32 *cs,
>>> + i915_reg_t reg, u32 offset, u32 dword_count)
>>> +{
>>> + uint32_t d;
>>> +
>>> + for (d = 0; d < dword_count; d++) {
>>> + *cs++ = INTEL_GEN(i915) >= 8 ?
>>> + MI_STORE_REGISTER_MEM_GEN8 : MI_STORE_REGISTER_MEM;
>>> + *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
>>> + *cs++ = intel_gt_scratch_offset(&i915->gt, offset) + 4 * d;
>>> + *cs++ = 0;
>>> + }
>>> +
>>> + return cs;
>>> +}
>>> +
>>> +static u32 *restore_register(struct drm_i915_private *i915, u32 *cs,
>>> + i915_reg_t reg, u32 offset, u32 dword_count)
>>> +{
>>> + uint32_t d;
>>> +
>>> + for (d = 0; d < dword_count; d++) {
>>> + *cs++ = INTEL_GEN(i915) >= 8 ?
>>> + MI_LOAD_REGISTER_MEM_GEN8 : MI_LOAD_REGISTER_MEM;
>>> + *cs++ = i915_mmio_reg_offset(reg);
>>> + *cs++ = intel_gt_scratch_offset(&i915->gt, offset);
>> are you missing + 4 * d in the above 2 lines?
> Whoops bad reviewer. Since these are the same two loops just with a
> different cmd...
> -Chris
>
Thanks Umesh!
I've merged these 2 function locally. I'm about to resend.
-Lionel
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