[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake part 2

[Patchwork]

== Series Details ==

Series: Tiger Lake part 2
URL   : https://patchwork.freedesktop.org/series/63670/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
4f24138130a1 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
05104c3c0561 drm/i915/tgl: select correct bit for port select
e617f60b4405 drm/i915/tgl: update ddi/tc clock_off bits
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:9752:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
+						       (tc_port) + 12 : \
+						       (tc_port) - PORT_TC4 + 21))

total: 0 errors, 0 warnings, 1 checks, 11 lines checked
57a1c831349d drm/i915/tgl: Add hpd interrupt handling
f2dae71692e9 drm/i915/tgl: Update north display hotplug detection to TGL connections
53ccf63d0767 drm/i915/tgl: handle DP aux interrupts
09bbb93143b0 drm/i915/dmc: Load DMC on TGL
68948c4cd8c6 drm/i915/tgl: Add DKL phy pll registers
eb6e1fade3e4 drm/i915/tgl: re-indent code to prepare for DKL changes
2ab94df17776 drm/i915/tgl: Add DKL phy pll state calculations
3b65df033d2d drm/i915/tgl: start adding the DKL PLLs to use on TC ports
afc14ee9b29d drm/i915/tgl: Add support for dkl pll write
75c99ba6ce4d drm/i915/gen12: add support for reading the timestamp frequency
208c82065cfd drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
86ca705881e4 drm/i915/tgl: Introduce initial Tigerlake Workarounds
4a3b203f6670 drm/i915/tgl: Implement Wa_1604555607
b7e6d7545812 drm/i915/tgl: Implement Wa_1406941453
155c1076b200 drm/i915/tgl: Define MOCS entries for Tigerlake
f0efc64bb91a drm/i915/tgl: Tigerlake only has global MOCS registers
5bc6743823d3 drm/i915: Move MOCS setup to intel_mocs.c
224b62268855 drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
a093f7155e48 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect