[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake part 2 (rev2)

[Patchwork]

== Series Details ==

Series: Tiger Lake part 2 (rev2)
URL   : https://patchwork.freedesktop.org/series/63670/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1399f5e0e588 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
7aeb531f6973 drm/i915/tgl: select correct bit for port select
61df67c27f47 drm/i915/tgl: update ddi/tc clock_off bits
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:9742:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
+						       (tc_port) + 12 : \
+						       (tc_port) - PORT_TC4 + 21))

total: 0 errors, 0 warnings, 1 checks, 11 lines checked
545774fac0b1 drm/i915/tgl: Add hpd interrupt handling
89b636156020 drm/i915/tgl: Update north display hotplug detection to TGL connections
b77732b3475a drm/i915/tgl: handle DP aux interrupts
d79bc42ba14e drm/i915/dmc: Load DMC on TGL
eba607ec684f drm/i915/tgl: Add DKL phy pll registers
bed7e1bf70ee drm/i915/tgl: re-indent code to prepare for DKL changes
fde555890199 drm/i915/tgl: Add DKL phy pll state calculations
21a4942ecadc drm/i915/tgl: start adding the DKL PLLs to use on TC ports
cf9e40f919cc drm/i915/tgl: Add support for dkl pll write
8839cfd99330 drm/i915/gen12: add support for reading the timestamp frequency
94f4cd6f0993 drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
c961a0a0ef25 drm/i915/tgl: Introduce initial Tigerlake Workarounds
e141194e47b0 drm/i915/tgl: Implement Wa_1604555607
21e1d03a7fc9 drm/i915/tgl: Implement Wa_1406941453
622babc7ad99 drm/i915/tgl: Define MOCS entries for Tigerlake
bbe66a71b6b7 drm/i915/tgl: Tigerlake only has global MOCS registers
2d16249077a4 drm/i915: Move MOCS setup to intel_mocs.c
f844f9561a03 drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
261c7e151c10 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect