[Intel-gfx] [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads

[Rafael Antognolli]

On Tue, Mar 05, 2019 at 01:48:26PM +0100, Michał Winiarski wrote:
> We assumed that the default preemption granularity is fine for ICL.
> Unfortunately, it turns out that some drivers don't support mid-thread
> preemption for compute workloads.
> If a workload that doesn't support mid-thread preemption gets mid-thread
> preempted, we're going to observe a GPU hang.
> While I'm here, let's also update the "workaround" naming.

Yeah, in Mesa we are not implementing the SIP, so we can't do
thread-level preemption yet and need the granularity to be no higher
than thread group level.

Acked-by: Rafael Antognolli <rafael.antognolli at intel.com>

> Signed-off-by: Michał Winiarski <michal.winiarski at intel.com>
> Cc: Anuj Phogat <anuj.phogat at intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Rafael Antognolli <rafael.antognolli at intel.com>
> Tested-by: Anuj Phogat <anuj.phogat at intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 89b4007d5200..2fba33509f4e 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -555,6 +555,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
>  			   GEN10_CACHE_MODE_SS,
>  			   0, /* write-only, so skip validation */
>  			   _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
> +
> +	/* WaDisableGPGPUMidThreadPreemption:icl */
> +	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
> +			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> +			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
>  }
>  
>  void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
> @@ -1162,8 +1167,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  				    GEN7_DISABLE_SAMPLER_PREFETCH);
>  	}
>  
> -	if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
> -		/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
> +	if (IS_GEN_RANGE(i915, 9, 11)) {
> +		/* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
>  		wa_masked_en(wal,
>  			     GEN7_FF_SLICE_CS_CHICKEN1,
>  			     GEN9_FFSC_PERCTX_PREEMPT_CTRL);
> -- 
> 2.20.1
>