[Intel-gfx] [PATCH v6 0/7] DC3CO Support for TGL

[Anshuman Gupta]

This is a new design proposal for DC3CO feature after disscussing
it with Ville and Imre.

This design uses a API tgl_set_target_dc_state() API
to switch between DC3CO and DC5 by using "DC off"
power well. Another major change in this design using page flip
frontbuffer flush call to allow DC3CO.

As part of DC3CO feature, it needs to configure and enable
TRANS_EXITLINE register which only needs to change when
transcoder/port is not enabled. It requires to configure and
enable it in full modeset sequence. Which requires to force
the modeset only at system bootup, with only eDP panel.

Tested this series on real H/W, DC3CO counter is validated
without any other issue observed.

Anshuman Gupta (7):
  drm/i915/tgl: Add DC3CO required register and bits
  drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
  drm/i915/tgl: Enable DC3CO state in "DC Off" power well
  drm/i915/tgl: Add helper function for DC3CO exitline.
  drm/i915/tgl: DC3CO PSR2 helper
  drm/i915/tgl: switch between dc3co and dc5 based on display idleness
  drm/i915/tgl: Add DC3CO counter in i915_dmc_info

 drivers/gpu/drm/i915/display/intel_display.c  |   7 +
 .../drm/i915/display/intel_display_power.c    | 305 ++++++++++++++++--
 .../drm/i915/display/intel_display_power.h    |  15 +
 .../gpu/drm/i915/display/intel_frontbuffer.c  |   1 +
 drivers/gpu/drm/i915/display/intel_psr.c      |  44 +++
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +
 drivers/gpu/drm/i915/i915_debugfs.c           |   6 +
 drivers/gpu/drm/i915/i915_drv.h               |   5 +
 drivers/gpu/drm/i915/i915_params.c            |   3 +-
 drivers/gpu/drm/i915/i915_reg.h               |  10 +
 drivers/gpu/drm/i915/intel_pm.c               |   2 +-
 drivers/gpu/drm/i915/intel_pm.h               |   2 +
 12 files changed, 372 insertions(+), 30 deletions(-)

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2.21.0