[Intel-gfx] [PATCH 2/3] drm/i915/display: Extract i965_read_luts()

[Jani Nikula]

On Fri, 06 Sep 2019, Swati Sharma <swati2.sharma at intel.com> wrote:
> For i965, add hw read out to create hw blob of gamma
> lut values.
>
> Review comments from old series:
> https://patchwork.freedesktop.org/series/58039/
>
> v4:  -No need to initialize *blob [Jani]
>      -Removed right shifts [Jani]
>      -Dropped dev local var [Jani]
> v5:  -Returned blob instead of assigning it internally
>       within the function [Ville]
>      -Renamed i965_get_color_config() to i965_read_lut() [Ville]
>      -Renamed i965_get_gamma_config_10p6() to i965_read_gamma_lut_10p6()
>       [Ville]
> v9:  -Typo and 80 character limit [Uma]
>      -Made read func para as const [Ville, Uma]
>      -Renamed i965_read_gamma_lut_10p6() to i965_read_lut_10p6() [Ville, Uma]
> v10: -Swapped ldw and udw while creating hw blob [Jani]
>
> Signed-off-by: Swati Sharma <swati2.sharma at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 43 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h            |  3 +++
>  2 files changed, 46 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 4d9a568..17199a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1570,6 +1570,48 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
>  }
>  
>  static struct drm_property_blob *
> +i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> +	enum pipe pipe = crtc->pipe;
> +	struct drm_property_blob *blob;
> +	struct drm_color_lut *blob_data;
> +	u32 i, val1, val2;
> +
> +	blob = drm_property_create_blob(&dev_priv->drm,
> +					sizeof(struct drm_color_lut) * lut_size,
> +					NULL);
> +	if (IS_ERR(blob))
> +		return NULL;
> +
> +	blob_data = blob->data;
> +
> +	for (i = 0; i < lut_size - 1; i++) {
> +		val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
> +		val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
> +
> +		blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
> +						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
> +		blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
> +						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
> +		blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
> +						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
> +	}

I missed it in my earlier review, need to get the last index from
PIPEGCMAX. See i965_load_lut_10p6().

With that added,

Reviewed-by: Jani Nikula <jani.nikula at intel.com>



> +
> +	return blob;
> +}
> +
> +static void i965_read_luts(struct intel_crtc_state *crtc_state)
> +{
> +	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> +		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> +	else
> +		crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
> +}
> +
> +static struct drm_property_blob *
>  ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> @@ -1672,6 +1714,7 @@ void intel_color_init(struct intel_crtc *crtc)
>  			dev_priv->display.color_check = i9xx_color_check;
>  			dev_priv->display.color_commit = i9xx_color_commit;
>  			dev_priv->display.load_luts = i965_load_luts;
> +			dev_priv->display.read_luts = i965_read_luts;
>  		} else {
>  			dev_priv->display.color_check = i9xx_color_check;
>  			dev_priv->display.color_commit = i9xx_color_commit;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 45ed96d..1e58c6d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3558,6 +3558,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _PALETTE_A		0xa000
>  #define _PALETTE_B		0xa800
>  #define _CHV_PALETTE_C		0xc000
> +#define PALETTE_RED_MASK        REG_GENMASK(23, 16)
> +#define PALETTE_GREEN_MASK      REG_GENMASK(15, 8)
> +#define PALETTE_BLUE_MASK       REG_GENMASK(7, 0)
>  #define PALETTE(pipe, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
>  				      _PICK((pipe), _PALETTE_A,		\
>  					    _PALETTE_B, _CHV_PALETTE_C) + \

-- 
Jani Nikula, Intel Open Source Graphics Center