[Intel-gfx] [PATCH 2/2] drm/i915/tgl: Register state context definition for Gen12

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2019-09-06 16:42:50)
> 
> On 9/6/19 5:23 AM, Mika Kuoppala wrote:
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -808,8 +808,11 @@ static void virtual_update_register_offsets(u32 *regs,
> >   {
> >       u32 base = engine->mmio_base;
> >   
> > +     GEM_WARN_ON(engine->class == COPY_ENGINE_CLASS);
> 
> Could use a comment up here to explain why, something like:
> 
> /* HW doesn't not support relative MMIO on COPY_ENGINE and we don't
> implement offset remap for all gens in SW because there is only 1
> instance */

What's the point of the check anyway? If the LRI are not using
relative addressing, we need to fixup the offsets. Aiui, it should just
be GEM_BUG_ON(intel_engine_has_relative_mmio(engine)). That we have only
a single instance in a particular class just means we never even call
the update function currently.
-Chris