[Intel-gfx] [PATCH v5 03/11] drm/i915/dsb: single register write function for DSB.

Animesh Manna animesh.manna at intel.com
Mon Sep 9 16:48:07 UTC 2019



On 9/9/2019 6:28 PM, Sharma, Shashank wrote:
>
> On 9/7/2019 4:37 PM, Animesh Manna wrote:
>> DSB support single register write through opcode 0x1. Generic
>> api created which accumulate all single register write in a batch
>> buffer and once DSB is triggered, it will program all the registers
>> at the same time.
>>
>> v1: Initial version.
>> v2: Unused macro removed and cosmetic changes done. (Shashank)
>>
>> Cc: Jani Nikula <jani.nikula at intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
>> Cc: Shashank Sharma <shashank.sharma at intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna at intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dsb.c | 30 ++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dsb.h |  9 +++++++
>>   2 files changed, 39 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
>> b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index cba5c8d37659..150be81fdfb3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -9,6 +9,13 @@
>>     #define DSB_BUF_SIZE    (2 * PAGE_SIZE)
>>   +/* DSB opcodes. */
>> +#define DSB_OPCODE_SHIFT        24
>> +#define DSB_OPCODE_MMIO_WRITE        0x1
>> +#define DSB_OPCODE_INDEXED_WRITE    0x9
>> +#define DSB_BYTE_EN            0xF
>> +#define DSB_BYTE_EN_SHIFT        20
>> +
>>   struct intel_dsb *
>>   intel_dsb_get(struct intel_crtc *crtc)
>>   {
>> @@ -46,6 +53,7 @@ intel_dsb_get(struct intel_crtc *crtc)
>>           goto err;
>>       }
>>       dsb->vma = vma;
>> +    dsb->free_pos = 0;
> This should be done in dsb_put();
>>     err:
>>       intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>> @@ -68,3 +76,25 @@ void intel_dsb_put(struct intel_dsb *dsb)
>>           mutex_unlock(&i915->drm.struct_mutex);
>>       }
>>   }
>> +
>> +void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 
>> val)
>> +{
>> +    struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
>> +    struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +    u32 *buf = dsb->cmd_buf;
>> +
>> +    if (!buf) {
>> +        I915_WRITE(reg, val);
>> +        return;
>> +    }
>> +
>> +    if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
>> +        DRM_DEBUG_KMS("DSB buffer overflow.\n");
>
> Lets remove this '.' in the end, to maintain consistency in the log.

Sure.

Regards,
Animesh



More information about the Intel-gfx mailing list