[Intel-gfx] [PATCH v3 02/23] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating

[Chris Wilson]

Quoting Lucas De Marchi (2019-08-23 09:20:34)
> From: Michel Thierry <michel.thierry at intel.com>
> 
> HCP/MFX power gating is disabled by default, turn it on for the vd units
> available. User space will also issue a MI_FORCE_WAKEUP properly to
> wake up proper subwell.
> 
> During driver load, init_clock_gating happens after device_info_init_mmio
> read the vdbox disable fuse register, so only present vd units will have
> these enabled.
> 
> BSpec: 14214
> HSDES: 1209977827
> Signed-off-by: Michel Thierry <michel.thierry at intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> Reviewed-by: Tony Ye <tony.ye at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
>  drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++++++-
>  2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a092b34c269d..02e1ef10c47e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8615,6 +8615,10 @@ enum {
>  #define   GEN9_PWRGT_MEDIA_STATUS_MASK         (1 << 0)
>  #define   GEN9_PWRGT_RENDER_STATUS_MASK                (1 << 1)
>  
> +#define POWERGATE_ENABLE                       _MMIO(0xa210)
> +#define    VDN_HCP_POWERGATE_ENABLE(n)         BIT(((n) * 2) + 3)
> +#define    VDN_MFX_POWERGATE_ENABLE(n)         BIT(((n) * 2) + 4)
> +
>  #define  GTFIFODBG                             _MMIO(0x120000)
>  #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV   (0x1f << 20)
>  #define    GT_FIFO_FREE_ENTRIES_CHV            (0x7f << 13)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 75ee027abb80..d3ea193cd093 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9078,6 +9078,22 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
>                    _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
>  }
>  
> +static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> +       u32 vd_pg_enable = 0;
> +       unsigned int i;
> +
> +       /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
> +       for (i = 0; i < I915_MAX_VCS; i++) {
> +               if (HAS_ENGINE(dev_priv, _VCS(i)))
> +                       vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
> +                                       VDN_MFX_POWERGATE_ENABLE(i);
> +       }
> +
> +       I915_WRITE(POWERGATE_ENABLE,
> +                  I915_READ(POWERGATE_ENABLE) | vd_pg_enable);

Is this display related at all?
-Chris