[Intel-gfx] [PATCH] drm/i915/tgl: Suspend pre-parser across GTT invalidations

[Chris Wilson]

Before we execute a batch, we must first issue any and all TLB
invalidations so that batch picks up the new page table entries.
Tigerlake's preparser is weakening our post-sync CS_STALL inside the
invalidate pipe-control and allowing the loading of the batch buffer
before we have setup its page table (and so it loads the wrong page and
executes indefinitely).

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
---
Suggestions welcome as this does not seem intended behaviour, so I
suspect there is a strong pipecontrol flag we are missing.
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a3f0e4999744..a9e690c303cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2796,11 +2796,14 @@ static int gen11_emit_flush_render(struct i915_request *request,
 		flags |= PIPE_CONTROL_QW_WRITE;
 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 
-		cs = intel_ring_begin(request, 6);
+		cs = intel_ring_begin(request, 8);
 		if (IS_ERR(cs))
 			return PTR_ERR(cs);
 
+		*cs++ = MI_ARB_CHECK | 1 << 8 | 1;
 		cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
+		*cs++ = MI_ARB_CHECK | 1 << 8;
+
 		intel_ring_advance(request, cs);
 	}
 
-- 
2.23.0