[Intel-gfx] [PATCH 07/14] drm/i915/tgl: Add support for dkl pll write

[Jani Nikula]

On Fri, 13 Sep 2019, Lucas De Marchi <lucas.de.marchi at gmail.com> wrote:
> On Fri, Sep 13, 2019 at 3:33 PM José Roberto de Souza
> <jose.souza at intel.com> wrote:
>>
>> From: Vandita Kulkarni <vandita.kulkarni at intel.com>
>>
>> Add a new function to write to dkl phy pll registers. As per the
>> bspec all the registers are read modify write.
>>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 ++++++++++++++++++-
>>  1 file changed, 64 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> index 424f9213c80d..afc9b609b63d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> @@ -3293,7 +3293,70 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
>>  static void dkl_pll_write(struct drm_i915_private *dev_priv,
>>                           struct intel_shared_dpll *pll)
>>  {
>> -       /* TODO */
>> +       struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
>> +       enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
>> +       u32 val;
>> +
>> +       /*
>> +        * All registers programmed here have the same HIP_INDEX_REG even
>> +        * though on different building block
>> +        */
>> +       I915_WRITE(HIP_INDEX_REG(tc_port), 0x2);
>> +
>> +       /* All the registers are RMW */
>
> I wish we could use intel_uncore_rmw() here to make this comment go
> away and make it simpler
> in general. But I understand the conversion to use uncore should still
> not be done in display. Should we add
> I195_RMW() meanwhile or it's not worth it? +Jani.

We have tons of code like this in display/ and in the big picture this
makes no difference. Please let's not add I915_RMW or anything such
while we do have a path forward with intel_de_{read,write,rwm}. It just
hasn't happened yet.

BR,
Jani.



>
> Lucas De Marchi
>
>> +       val = I915_READ(DKL_REFCLKIN_CTL(tc_port));
>> +       val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
>> +       val |= hw_state->mg_refclkin_ctl;
>> +       I915_WRITE(DKL_REFCLKIN_CTL(tc_port), val);
>> +
>> +       val = I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
>> +       val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
>> +       val |= hw_state->mg_clktop2_coreclkctl1;
>> +       I915_WRITE(DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
>> +
>> +       val = I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
>> +       val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
>> +              MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
>> +              MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
>> +              MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
>> +       val |= hw_state->mg_clktop2_hsclkctl;
>> +       I915_WRITE(DKL_CLKTOP2_HSCLKCTL(tc_port), val);
>> +
>> +       val = I915_READ(DKL_PLL_DIV0(tc_port));
>> +       val &= ~(DKL_PLL_DIV0_INTEG_COEFF_MASK |
>> +               DKL_PLL_DIV0_PROP_COEFF_MASK |
>> +               DKL_PLL_DIV0_FBPREDIV_MASK |
>> +               DKL_PLL_DIV0_FBDIV_INT_MASK);
>> +       val |= hw_state->mg_pll_div0;
>> +       I915_WRITE(DKL_PLL_DIV0(tc_port), val);
>> +
>> +       val = I915_READ(DKL_PLL_DIV1(tc_port));
>> +       val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
>> +                DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
>> +       val |= hw_state->mg_pll_div1;
>> +       I915_WRITE(DKL_PLL_DIV1(tc_port), val);
>> +
>> +       val = I915_READ(DKL_PLL_SSC(tc_port));
>> +       val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
>> +               DKL_PLL_SSC_STEP_LEN_MASK |
>> +               DKL_PLL_SSC_STEP_NUM_MASK |
>> +               DKL_PLL_SSC_EN);
>> +       val |= hw_state->mg_pll_ssc;
>> +       I915_WRITE(DKL_PLL_SSC(tc_port), val);
>> +
>> +       val = I915_READ(DKL_PLL_BIAS(tc_port));
>> +       val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
>> +               DKL_PLL_BIAS_FBDIV_FRAC_MASK);
>> +       val |= hw_state->mg_pll_bias;
>> +       I915_WRITE(DKL_PLL_BIAS(tc_port), val);
>> +
>> +       val = I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
>> +       val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
>> +               DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
>> +       val |= hw_state->mg_pll_tdc_coldst_bias;
>> +       I915_WRITE(DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
>> +
>> +       POSTING_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
>>  }
>>
>>  static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
>> --
>> 2.23.0
>>
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-- 
Jani Nikula, Intel Open Source Graphics Center