[Intel-gfx] [PATCH] drm/i915: Adding YUV444 packed format support for skl+

[Matt Roper]

On Mon, Sep 16, 2019 at 10:39:55AM -0700, Bob Paauwe wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> 
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
> 
> v2: Edited commit message, removed redundant whitespaces.
> 
> v3: Fixed fallthrough logic for the format switch cases.
> 
> v4: Yet again fixed fallthrough logic, to reuse code from other case
>     labels.
> 
> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
> 
> v6: Removed unneeded initializer for new XYUV format.
> 
> v7: Added scaling support for DRM_FORMAT_XYUV
> 
> v8: Edited commit message to be more clear about skl+, renamed
>     PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
>     doesn't support per-pixel alpha. Fixed minor code issues.
> 
> v9: Moved DRM format check to proper place in intel_framebuffer_init.
> 
> v10: Added missing XYUV format to sprite planes for skl+.
> 
> v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888.
> 
> v12: Fixed rebase conflicts
> 
> V13: Rebased.
> 
> v12:
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe at intel.com>

The rebase of https://patchwork.freedesktop.org/patch/261142/ looks
correct, so

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

but it looks like we'll also need an update to IGT before we merge this,
otherwise it will break CI testing for kms_plane and kms_plane_scaling.

IGT needs this new format added to formats[] in lib/igt_color_encoding.c
so that lookup_fourcc() won't return failures.


Matt

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
>  drivers/gpu/drm/i915/display/intel_sprite.c  | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  3 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 12bb8f951edf..7b9fb9e7893d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2978,6 +2978,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>  		return DRM_FORMAT_RGB565;
>  	case PLANE_CTL_FORMAT_NV12:
>  		return DRM_FORMAT_NV12;
> +	case PLANE_CTL_FORMAT_XYUV:
> +		return DRM_FORMAT_XYUV8888;
>  	case PLANE_CTL_FORMAT_P010:
>  		return DRM_FORMAT_P010;
>  	case PLANE_CTL_FORMAT_P012:
> @@ -3988,6 +3990,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
>  	case DRM_FORMAT_XRGB16161616F:
>  	case DRM_FORMAT_ARGB16161616F:
>  		return PLANE_CTL_FORMAT_XRGB_16161616F;
> +	case DRM_FORMAT_XYUV8888:
> +		return PLANE_CTL_FORMAT_XYUV;
>  	case DRM_FORMAT_YUYV:
>  		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
>  	case DRM_FORMAT_YVYU:
> @@ -5581,6 +5585,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XYUV8888:
>  	case DRM_FORMAT_P010:
>  	case DRM_FORMAT_P012:
>  	case DRM_FORMAT_P016:
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 7a7078d0ba23..b30809b28e17 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2015,6 +2015,7 @@ static const u32 skl_plane_formats[] = {
>  	DRM_FORMAT_YVYU,
>  	DRM_FORMAT_UYVY,
>  	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_XYUV8888,
>  };
>  
>  static const u32 skl_planar_formats[] = {
> @@ -2031,6 +2032,7 @@ static const u32 skl_planar_formats[] = {
>  	DRM_FORMAT_UYVY,
>  	DRM_FORMAT_VYUY,
>  	DRM_FORMAT_NV12,
> +	DRM_FORMAT_XYUV8888,
>  };
>  
>  static const u32 glk_planar_formats[] = {
> @@ -2273,6 +2275,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XYUV8888:
>  	case DRM_FORMAT_P010:
>  	case DRM_FORMAT_P012:
>  	case DRM_FORMAT_P016:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bf37ecebc82f..20cdffc23a95 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6656,7 +6656,7 @@ enum {
>  #define   PLANE_CTL_FORMAT_P012			(5 << 24)
>  #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
>  #define   PLANE_CTL_FORMAT_P016			(7 << 24)
> -#define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
> +#define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
>  #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
>  #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
>  #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795