[Intel-gfx] [PATCH v2 00/13] TGL TC enabling v2

[José Roberto de Souza]

Version 2 of https://patchwork.freedesktop.org/series/66695/

Most important change is the drop of the usage of the hardcoded table with the
registers values to DKL PLL registers, a bug in the calculation was fixed and
a step that is not on the BSpec was added to make it work on HW and match with
hardcoded table.
Also addressed Lucas comments, all of those noted in the changelog of each
patch.

Clinton A Taylor (4):
  drm/i915/tgl: Add missing ddi clock select during DP init sequence
  drm/i915/tgl/pll: Set update_active_dpll
  drm/i915/tgl: TC helper function to return pin mapping
  drm/i915/tgl: Add dkl phy programming sequences

José Roberto de Souza (5):
  drm/i915/tgl: Finish modular FIA support on registers
  drm/i915/icl: Unify disable and enable phy clock gating functions
  drm/i915/tgl: Check the UC health of tc controllers after power on
  drm/i915/tgl: Add dkl phy pll calculations
  drm/i915/tgl: Fix dkl link training

Lucas De Marchi (2):
  drm/i915/tgl: Add initial dkl pll support
  drm/i915/tgl: initialize TC and TBT ports

Vandita Kulkarni (2):
  drm/i915/tgl: Add dkl phy registers
  drm/i915/tgl: Add support for dkl pll write

 drivers/gpu/drm/i915/display/intel_ddi.c      | 323 ++++++++++++++---
 drivers/gpu/drm/i915/display/intel_display.c  |   7 +-
 .../drm/i915/display/intel_display_power.c    |  13 +
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 332 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_tc.c       |  61 +++-
 drivers/gpu/drm/i915/display/intel_tc.h       |   2 +
 drivers/gpu/drm/i915/i915_reg.h               | 195 +++++++++-
 8 files changed, 788 insertions(+), 146 deletions(-)

-- 
2.23.0