[Intel-gfx] [PATCH] drm/i915: Set proper voltage level for 324 and 326.4 cdclks

[Souza, Jose]

On Thu, 2019-09-05 at 13:35 -0700, Matt Roper wrote:
> These new cdclk values should be accounted for in the voltage level
> selection (we can use the same voltage level as 307.2 and 312 rather
> than bumping up up to the next higher level).

Just checked this page and there is change draft in progress, lets wait
for the official update to review this one.

> 
> Bspec: 21809
> Cc: José Roberto de Souza <jose.souza at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
> The EHL and TGL parts of the bspec haven't actually updated their
> voltage requirement tables to mention the new cdclk frequencies at
> all,
> so I'm assuming here that those platforms will follow ICL's lead of
> using the same voltage level as the 307/312 clocks.  I've filed a
> ticket
> with the hardware team to confirm this; we should hold off on
> actually
> merging these changes until we get a response.
> 
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d3e56628af70..1329d3e60e26 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1833,7 +1833,7 @@ static int icl_calc_cdclk_pll_vco(struct
> drm_i915_private *dev_priv, int cdclk)
>  static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv,
> int cdclk)
>  {
>  	if (IS_ELKHARTLAKE(dev_priv)) {
> -		if (cdclk > 312000)
> +		if (cdclk > 326400)
>  			return 2;
>  		else if (cdclk > 180000)
>  			return 1;
> @@ -1842,7 +1842,7 @@ static u8 icl_calc_voltage_level(struct
> drm_i915_private *dev_priv, int cdclk)
>  	} else {
>  		if (cdclk > 556800)
>  			return 2;
> -		else if (cdclk > 312000)
> +		else if (cdclk > 326400)
>  			return 1;
>  		else
>  			return 0;