[Intel-gfx] [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts()
Jani Nikula
jani.nikula at intel.com
Fri Sep 20 10:24:14 UTC 2019
On Thu, 19 Sep 2019, Swati Sharma <swati2.sharma at intel.com> wrote:
> For icl+, have hw read out to create hw blob of gamma
> lut values. icl+ platforms supports multi segmented gamma
> mode by default, add hw lut creation for this mode.
>
> This will be used to validate gamma programming using dsb
> (display state buffer) which is a tgl specific feature.
>
> Following are the main changes done in this patch:
> 1. gamma_enable checks made specific to platform func()
> since icl doeesn't support that and enable gamma through mode
> 2. lut[0] and lut[8] enteries should be same superfine and coarse;
> superfine and fine segments respectively, checked twice-no harm
> 3. Removed temporary lut
> 4. Coarse segment interpolated gamma values loop start from 2
> instead of 0, since actual h/w values started getting overrided.
>
> v2: -readout code for multisegmented gamma has to come
> up with some intermediate entries that aren't preserved
> in hardware (Jani N)
> -linear interpolation (Ville)
> -moved common code to check gamma_enable to specific funcs,
> since icl doesn't support that
> v3: -use u16 instead of __u16 [Jani N]
> -used single lut [Jani N]
> -improved and more readable for loops [Jani N]
> -read values directly to actual locations and then fill gaps [Jani N]
> -moved cleaning to patch 1 [Jani N]
> -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
> make it similar to icl_load_luts()
> -renamed icl_compute_interpolated_gamma_blob() to
> icl_compute_interpolated_gamma_lut_values() more sensible, I guess
>
> Signed-off-by: Swati Sharma <swati2.sharma at intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 216 +++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 7 +
> 2 files changed, 208 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 765482d..ad548ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1371,6 +1371,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>
> static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1384,6 +1387,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> return 0;
>
> @@ -1400,6 +1406,9 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> return 10;
> else
> @@ -1408,6 +1417,9 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1419,21 +1431,39 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> }
> }
>
> +static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
> +{
> + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
> + return 0;
> +
> + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> + return 16;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +
> +}
> +
> int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (!crtc_state->gamma_enable)
> - return 0;
> -
> if (HAS_GMCH(dev_priv)) {
> if (IS_CHERRYVIEW(dev_priv))
> return chv_gamma_precision(crtc_state);
> else
> return i9xx_gamma_precision(crtc_state);
> } else {
> - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 11)
> + return icl_gamma_precision(crtc_state);
> + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> return glk_gamma_precision(crtc_state);
> else if (IS_IRONLAKE(dev_priv))
> return ilk_gamma_precision(crtc_state);
> @@ -1464,6 +1494,30 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
> return true;
> }
>
> +static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
> + struct drm_color_lut *lut2,
> + int lut_size, u32 err)
> +{
> + int i;
> +
> + for (i = 0; i < 9; i++) {
> + if (!err_check(&lut1[i], &lut2[i], err))
> + return false;
> + }
> +
> + for (i = 1; i < 257; i++) {
> + if (!err_check(&lut1[i * 8], &lut2[i * 8], err))
> + return false;
> + }
> +
> + for (i = 0; i < 256; i++) {
> + if (!err_check(&lut1[i * 8 * 128], &lut2[i * 8 * 128], err))
> + return false;
> + }
So apparently we're facing some issues with the readout of the relevant
registers. I suggest we wrap the above two loops in
#if 0
#endif
with a comment explaining why.
I don't much like this, but having *some* validation of this is better
than *no* validation.
BR,
Jani.
> +
> + return true;
> +}
> +
> bool intel_color_lut_equal(struct drm_property_blob *blob1,
> struct drm_property_blob *blob2,
> u32 gamma_mode, u32 bit_precision)
> @@ -1482,16 +1536,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
> lut_size2 = drm_color_lut_size(blob2);
>
> /* check sw and hw lut size */
> - switch (gamma_mode) {
> - case GAMMA_MODE_MODE_8BIT:
> - case GAMMA_MODE_MODE_10BIT:
> - if (lut_size1 != lut_size2)
> - return false;
> - break;
> - default:
> - MISSING_CASE(gamma_mode);
> - return false;
> - }
> + if (lut_size1 != lut_size2)
> + return false;
>
> lut1 = blob1->data;
> lut2 = blob2->data;
> @@ -1499,13 +1545,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
> err = 0xffff >> bit_precision;
>
> /* check sw and hw lut entry to be equal */
> - switch (gamma_mode) {
> + switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
> case GAMMA_MODE_MODE_8BIT:
> case GAMMA_MODE_MODE_10BIT:
> if (!intel_color_lut_entry_equal(lut1, lut2,
> lut_size2, err))
> return false;
> break;
> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> + if (!intel_color_lut_entry_multi_equal(lut1, lut2,
> + lut_size2, err))
> + return false;
> + break;
> default:
> MISSING_CASE(gamma_mode);
> return false;
> @@ -1745,6 +1796,140 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
> crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> }
>
> +static u16 cal_step_size(u16 end_val, u16 start_val, int steps)
> +{
> + return ((end_val - start_val) / steps);
> +}
> +
> +static struct drm_color_lut *
> +icl_compute_interpolated_gamma_lut_values(struct drm_color_lut *lut, u32 lut_size)
> +{
> + u16 red_step_size, green_step_size, blue_step_size;
> + int start, end, steps;
> + int i, j;
> +
> + for (i = 1; i < 257 - 1; i++) {
> + start = i * 8;
> + end = (i + 1) * 8;
> + steps = end - start;
> +
> + red_step_size = cal_step_size(lut[end].red, lut[start].red, steps);
> + green_step_size = cal_step_size(lut[end].green, lut[start].green, steps);
> + blue_step_size = cal_step_size(lut[end].blue, lut[start].blue, steps);
> +
> + for (j = start + 1; j < end; j++) {
> + lut[j].red = lut[j - 1].red + red_step_size;
> + lut[j].green = lut[j - 1].green + green_step_size;
> + lut[j].blue = lut[j - 1].blue + blue_step_size;
> +
> + i++;
> + }
> + }
> +
> + for (i = 2; i < 256 - 1; i++) {
> + start = i * 8 * 128;
> + end = (i + 1) * 8 * 128;
> + steps = end - start;
> +
> + red_step_size = cal_step_size(lut[end].red, lut[start].red, steps);
> + green_step_size = cal_step_size(lut[end].green, lut[start].green, steps);
> + blue_step_size = cal_step_size(lut[end].blue, lut[start].blue, steps);
> +
> + for (j = start + 1; j < end; j++) {
> + lut[j].red = lut[j - 1].red + red_step_size;
> + lut[j].green = lut[j - 1].green + green_step_size;
> + lut[j].blue = lut[j - 1].blue + blue_step_size;
> +
> + i++;
> + }
> + }
> +
> + return lut;
> +}
> +
> +static struct drm_property_blob *
> +icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> + enum pipe pipe = crtc->pipe;
> + struct drm_property_blob *blob;
> + struct drm_color_lut *blob_data;
> + u32 i, val1, val2;
> +
> + blob = drm_property_create_blob(&dev_priv->drm,
> + sizeof(struct drm_color_lut) * lut_size,
> + NULL);
> + if (IS_ERR(blob))
> + return NULL;
> +
> + blob_data = blob->data;
> +
> + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> +
> + for (i = 0; i < 9; i++) {
> + val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> + val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> +
> + blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> + blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> + blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> + }
> +
> + I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> +
> + for (i = 1; i < 257; i++) {
> + val1 = I915_READ(PREC_PAL_DATA(pipe));
> + val2 = I915_READ(PREC_PAL_DATA(pipe));
> +
> + blob_data[i * 8].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> + blob_data[i * 8].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> + blob_data[i * 8].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> + }
> +
> + for (i = 0; i < 256; i++) {
> + val1 = I915_READ(PREC_PAL_DATA(pipe));
> + val2 = I915_READ(PREC_PAL_DATA(pipe));
> +
> + blob_data[i * 8 * 128].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> + blob_data[i * 8 * 128].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> + blob_data[i * 8 * 128].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> + }
> +
> + blob_data[lut_size - 1].red = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> + I915_READ(PREC_PAL_GC_MAX(pipe, 0)));
> + blob_data[lut_size - 1].green = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> + I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
> + blob_data[lut_size - 1].blue = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> + I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
> +
> + blob_data = icl_compute_interpolated_gamma_lut_values(blob_data, lut_size);
> +
> + return blob;
> +}
> +
> +static void icl_read_luts(struct intel_crtc_state *crtc_state)
> +{
> + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> + GAMMA_MODE_MODE_8BIT)
> + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> + GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
> + crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state);
> + else
> + crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> +}
> +
> void intel_color_init(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -1788,6 +1973,7 @@ void intel_color_init(struct intel_crtc *crtc)
>
> if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.load_luts = icl_load_luts;
> + dev_priv->display.read_luts = icl_read_luts;
> } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> dev_priv->display.load_luts = glk_load_luts;
> dev_priv->display.read_luts = glk_read_luts;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bf37ece..844dd62 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10378,6 +10378,7 @@ enum skl_power_gate {
>
> #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
> #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
> +#define PREC_PAL_GC_MAX_RGB_MASK REG_GENMASK(15, 0)
> #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
> #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
> #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
> @@ -10401,6 +10402,12 @@ enum skl_power_gate {
>
> #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
> #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
> +#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
> +#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
> +#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
> +#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
> +#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
> +#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
>
> #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
> _PAL_PREC_MULTI_SEG_INDEX_A, \
--
Jani Nikula, Intel Open Source Graphics Center
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