[Intel-gfx] [PATCH] drm/i915/tgl: Add memory type decoding for bandwidth checking

[Ville Syrjälä]

On Thu, Sep 19, 2019 at 03:16:40PM -0700, James Ausmus wrote:
> The memory type values have changed in TGL, so we need to translate them
> differently than ICL.
> 
> BSpec: 53998
> 
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> Signed-off-by: James Ausmus <james.ausmus at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 59 ++++++++++++++++++-------
>  1 file changed, 43 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 688858ebe4d0..11224d9a6752 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -35,22 +35,49 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
>  	if (ret)
>  		return ret;
>  
> -	switch (val & 0xf) {
> -	case 0:
> -		qi->dram_type = INTEL_DRAM_DDR4;
> -		break;
> -	case 1:
> -		qi->dram_type = INTEL_DRAM_DDR3;
> -		break;
> -	case 2:
> -		qi->dram_type = INTEL_DRAM_LPDDR3;
> -		break;
> -	case 3:
> -		qi->dram_type = INTEL_DRAM_LPDDR3;

This should be LPDDR4 actually. Doesn't really matter but would be nice
to fix as well.

> -		break;
> -	default:
> -		MISSING_CASE(val & 0xf);
> -		break;
> +	if (IS_GEN(dev_priv, 12)) {
> +		switch (val & 0xf) {
> +		case 0:
> +			qi->dram_type = INTEL_DRAM_DDR4;
> +			break;
> +		case 3:
> +			qi->dram_type = INTEL_DRAM_LPDDR4;
> +			break;
> +		case 4:
> +			qi->dram_type = INTEL_DRAM_DDR3;
> +			break;
> +		case 5:
> +			qi->dram_type = INTEL_DRAM_LPDDR3;
> +			break;
> +		case 1:
> +		case 2:
> +			/* Unimplemented */

Seems pointless to list these.

The numbers match bspec. Unfortunatley I can't get tgl
configdb to cooperate so can't double check against the
MC register definition.

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> +			/* fall through */
> +		default:
> +			MISSING_CASE(val & 0xf);
> +			break;
> +		}
> +	} else if (IS_GEN(dev_priv, 11)) {
> +		switch (val & 0xf) {
> +		case 0:
> +			qi->dram_type = INTEL_DRAM_DDR4;
> +			break;
> +		case 1:
> +			qi->dram_type = INTEL_DRAM_DDR3;
> +			break;
> +		case 2:
> +			qi->dram_type = INTEL_DRAM_LPDDR3;
> +			break;
> +		case 3:
> +			qi->dram_type = INTEL_DRAM_LPDDR3;
> +			break;
> +		default:
> +			MISSING_CASE(val & 0xf);
> +			break;
> +		}
> +	} else {
> +		MISSING_CASE(INTEL_GEN(dev_priv));
> +		qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
>  	}
>  
>  	qi->num_channels = (val & 0xf0) >> 4;
> -- 
> 2.22.1

-- 
Ville Syrjälä
Intel