[Intel-gfx] [PATCH v3 8/9] drm/i915/tgl: Return the mg/dkl pll as DDI clock for new TC ports

[Lucas De Marchi]

On Mon, Sep 23, 2019 at 12:55 PM José Roberto de Souza
<jose.souza at intel.com> wrote:
>
> TGL added 2 more TC ports that currently are not being handled by
> icl_pll_to_ddi_clk_sel(), so adding those.
>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> Reported-by: Imre Deak <imre.deak at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>

I don't think we use them, but for completeness seem ok (so we don't
keep thinking why we didn't
add it to match the spec)... maybe future sku's make use of them, so
better match the spec:

Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 938639675529..e50f492b3100 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1076,6 +1076,8 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
>         case DPLL_ID_ICL_MGPLL2:
>         case DPLL_ID_ICL_MGPLL3:
>         case DPLL_ID_ICL_MGPLL4:
> +       case DPLL_ID_TGL_MGPLL5:
> +       case DPLL_ID_TGL_MGPLL6:
>                 return DDI_CLK_SEL_MG;
>         }
>  }
> --
> 2.23.0
>
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-- 
Lucas De Marchi