[Intel-gfx] [PATCH v3 4/9] drm/i915/tgl: Add dkl phy programming sequences
Imre Deak
imre.deak at intel.com
Tue Sep 24 13:00:06 UTC 2019
On Mon, Sep 23, 2019 at 03:02:54PM -0700, Lucas De Marchi wrote:
> On Mon, Sep 23, 2019 at 12:55 PM José Roberto de Souza
> <jose.souza at intel.com> wrote:
> > [...]
>
> > + ln1 &= ~(DKL_DP_MODE_CFG_DP_X1_MODE | DKL_DP_MODE_CFG_DP_X2_MODE);
> > +
> > + lane_mask = intel_tc_port_get_lane_mask(intel_dig_port); /* DPX4TXLATC */
> > + pin_mask = intel_tc_port_get_pin_assignment_mask(intel_dig_port); /* DPPATC */
> > +
> > + switch (pin_mask) {
>
> From a quick look to the table, we don't change based on pin_mask, but
> rather based on lane_mask, just like for MG.
There are differences, for instance pin_mask=0x4,0x6/lane_mask=0x3 vs.
pin_mask=0x2/lane_mask=0x3.
> Btw, lane_mask is unused in this function now and we don't get a
> warning just because it's misused in a
> MISSING_CASE() below.
>
> The values do change based on width, but I'm not sure why MG doesn't
> need to take that into account.
Yes, looks like crtc_state->lane_count should be considered. Not sure
why the MG version doesn't do that either, I assume it was an addition
to BSpec only after the function was added. The same applies to
pin_mask.
> +Imre Deak
>
> Lucas De Marchi
>
> > + case 0x0:
> > + if (num_lanes == 1) {
> > + ln1 |= DKL_DP_MODE_CFG_DP_X1_MODE;
> > + } else {
> > + ln0 |= DKL_DP_MODE_CFG_DP_X2_MODE;
> > + ln1 |= DKL_DP_MODE_CFG_DP_X2_MODE;
> > + }
> > + break;
> > + case 0x1:
> > + if (num_lanes == 4) {
> > + ln0 |= DKL_DP_MODE_CFG_DP_X2_MODE;
> > + ln1 |= DKL_DP_MODE_CFG_DP_X2_MODE;
> > + }
> > + break;
> > + case 0x2:
> > + if (num_lanes == 2) {
> > + ln0 |= DKL_DP_MODE_CFG_DP_X2_MODE;
> > + ln1 |= DKL_DP_MODE_CFG_DP_X2_MODE;
> > + }
> > + break;
> > + case 0x3:
> > + case 0x5:
> > + if (num_lanes == 1) {
> > + ln0 |= DKL_DP_MODE_CFG_DP_X1_MODE;
> > + ln1 |= DKL_DP_MODE_CFG_DP_X1_MODE;
> > + } else {
> > + ln0 |= DKL_DP_MODE_CFG_DP_X2_MODE;
> > + ln1 |= DKL_DP_MODE_CFG_DP_X2_MODE;
> > + }
> > + break;
> > + case 0x4:
> > + case 0x6:
> > + if (num_lanes == 1) {
> > + ln0 |= DKL_DP_MODE_CFG_DP_X1_MODE;
> > + ln1 |= DKL_DP_MODE_CFG_DP_X1_MODE;
> > + } else {
> > + ln0 |= DKL_DP_MODE_CFG_DP_X2_MODE;
> > + ln1 |= DKL_DP_MODE_CFG_DP_X2_MODE;
> > + }
> > + break;
> > + default:
> > + MISSING_CASE(lane_mask);
> > + }
> > + break;
> > +
> > + case TC_PORT_LEGACY:
> > + ln0 |= DKL_DP_MODE_CFG_DP_X1_MODE | DKL_DP_MODE_CFG_DP_X2_MODE;
> > + ln1 |= DKL_DP_MODE_CFG_DP_X1_MODE | DKL_DP_MODE_CFG_DP_X2_MODE;
> > + break;
> > +
> > + default:
> > + MISSING_CASE(intel_dig_port->tc_mode);
> > + return;
> > + }
> > +
> > + I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
> > + I915_WRITE(DKL_DP_MODE(tc_port), ln0);
> > + I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
> > + I915_WRITE(DKL_DP_MODE(tc_port), ln1);
> > +}
> > +
> > static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state)
> > {
> > @@ -3218,7 +3431,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > dig_port->ddi_io_power_domain);
> >
> > /* 6. */
> > - icl_program_mg_dp_mode(dig_port);
> > + tgl_program_dkl_dp_mode(dig_port);
> >
> > /*
> > * 7.a - Steps in this function should only be executed ov´er MST
> > @@ -3231,10 +3444,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > intel_ddi_config_transcoder_func(crtc_state);
> >
> > /* 7.d */
> > - icl_phy_set_clock_gating(dig_port, false);
> > + tgl_phy_set_clock_gating(dig_port, false);
> >
> > /* 7.e */
> > - icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> > + tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> > encoder->type);
> >
> > /* 7.f */
> > @@ -3266,6 +3479,15 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > /* 7.k */
> > intel_dp_stop_link_train(intel_dp);
> >
> > + /*
> > + * TODO: enable clock gating
> > + *
> > + * It is not written in DP enabling sequence but "PHY Clockgating
> > + * programming" states that clock gating should be enabled after the
> > + * link training but doing so causes all the following trainings to fail
> > + * so not enabling it for now.
> > + */
> > +
> > /* 7.l */
> > intel_ddi_enable_fec(encoder, crtc_state);
> > intel_dsc_enable(encoder, crtc_state);
> > @@ -3371,9 +3593,15 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> > intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
> >
> > icl_program_mg_dp_mode(dig_port);
> > - icl_phy_set_clock_gating(dig_port, false);
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + tgl_phy_set_clock_gating(dig_port, false);
> > + else
> > + icl_phy_set_clock_gating(dig_port, false);
> >
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> > + level, INTEL_OUTPUT_HDMI);
> > + else if (INTEL_GEN(dev_priv) == 11)
> > icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
> > level, INTEL_OUTPUT_HDMI);
> > else if (IS_CANNONLAKE(dev_priv))
> > @@ -3383,7 +3611,10 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> > else
> > intel_prepare_hdmi_ddi_buffers(encoder, level);
> >
> > - icl_phy_set_clock_gating(dig_port, true);
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + tgl_phy_set_clock_gating(dig_port, true);
> > + else
> > + icl_phy_set_clock_gating(dig_port, true);
> >
> > if (IS_GEN9_BC(dev_priv))
> > skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
> > --
> > 2.23.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Lucas De Marchi
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