[Intel-gfx] [PATCH v3 7/9] drm/i915/tgl: Fix dkl link training

[Imre Deak]

On Mon, Sep 23, 2019 at 12:55:11PM -0700, José Roberto de Souza wrote:
> Link training is failling when running link at 2.7GHz and 1.62GHz and
> following BSpec pll algorithm.
> 
> Comparing the values calculated and the ones from the reference table
> it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set
> to 5. For DP ports ICL mg pll algorithm sets it to 10 or 5 based on
> div2 value, that matches with dkl hardcoded table.
> 
> So implementing this way as it proved to work in HW and leaving a
> comment so we know why it do not match BSpec.
> 
> Issue reported on BSpec 49204.
> 
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 496df4095a21..3c881d4cf973 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2631,7 +2631,12 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>  
>  			if (div2 >= 2) {
>  				if (is_dkl) {
> -					a_divratio = 5;
> +					/*
> +					 * Note: a_divratio not matching TGL
> +					 * BSpec algorithm but matching
> +					 * hardcoded values and working on HW
> +					 */
> +					a_divratio = 10;

Yes, matches the hardcoded values for CLKTOP2_HSCLKCTL/CORECLKCTL1, with
the exception that the hardcoded value for CLKTOP2_HSCLKCTL 5p4 is also
incorrect wrt. div2 within that (should be 1 but it's 2).

However we don't have any hardcoded values in Bspec for HDMI except for
the 5.94Gbps/div2=1 case. So until otherwise proven, for HDMI/div2>=2 I
wouldn't change the value, rather have the same logic as for ICL that is
is_dp ? 10 : 5;

>  					tlinedrv = 1;
>  				} else {
>  					a_divratio = is_dp ? 10 : 5;
> -- 
> 2.23.0
> 
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