[Intel-gfx] [PATCH 4/6] drm/i915: Add definitions for MI_MATH command

[Chris Wilson]

Quoting Michał Winiarski (2019-09-26 11:06:33)
> We can use it in i915 for updating parts of unmasked registers from
> within a batch. We're also adding Gen8+ versions of CS_GPR registers
> (aka MI_MATH_REG in the coprocessor).
> 
> Signed-off-by: Michał Winiarski <michal.winiarski at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>

Checked against mesa's xml for convenience,
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>

> ---
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 24 ++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
>  2 files changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 9211b1ad401b..26c286bc9625 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -241,6 +241,30 @@
>  #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH               (1<<0)
>  #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
>  
> +#define MI_MATH(x)                     MI_INSTR(0x1A, (x)-1)
> +#define MI_MATH_INSTR(opcode, op1, op2) (((opcode) << 20) | \
> +                                        ((op1) << 10) | (op2))

Perhaps this would benefit from a touch of REG_FIELD for value checking.
-Chris