[Intel-gfx] [PATCH] drm/i915: Delegate our irq handler to a thread

[Sebastian Andrzej Siewior]

On 2019-09-26 16:44:33 [+0100], Chris Wilson wrote:
> > It's all edge interrupts -- although for gen2/3 my memory is hazy. But
> > the GPU (circa gen6) can generate more than enough interrupts to saturate
> > a CPU.
> 
> So everything older than gen5 has MSI disabled it appears and needs
> ONESHOT.

Also ACPI/PCI-quirks may decide that MSI is broken on the system and
disable it.

If you end up with a shared handler, you can't mix ONESHOT among the
handlers. So either all have that flag set or none of them.
In that case you need to provide a tiny primary handler which just
disables the IRQ (in the HW) and the threaded handler has to enable it
again (at the end of its routine).

> -Chris

Sebastian