[Intel-gfx] [PATCH v9 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info

[Imre Deak]

On Thu, Sep 26, 2019 at 08:26:21PM +0530, Anshuman Gupta wrote:
> Adding DC3CO counter in i915_dmc_info debugfs will be
> useful for DC3CO validation.
> DMC firmware uses DMC_DEBUG3 register as DC3CO counter
> register on TGL, as per B.Specs DMC_DEBUG3 is general
> purpose register.
> 
> Cc: Jani Nikula <jani.nikula at intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> Cc: Animesh Manna <animesh.manna at intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
>  drivers/gpu/drm/i915/i915_reg.h     | 2 ++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index b5b449a88cf1..8a16bbd31212 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2407,6 +2407,12 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
>  		   CSR_VERSION_MINOR(csr->version));
>  
> +	/*
> +	 * TGL DMC f/w uses DMC_DEBUG3 register for DC3CO counter.
> +	 */

The above is obvious from the code itself, so we don't need a comment
for it. Please also consider removing all other comments in the patchset
that state only what is obvious from the code.

> +	if (IS_TIGERLAKE(dev_priv))

The above should match the check in get_allowed_dc_mask().

> +		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
> +
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
>  		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3ee9720af207..af810f6ed652 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7263,6 +7263,8 @@ enum {
>  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
>  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
>  
> +#define DMC_DEBUG3		_MMIO(0x101090)
> +
>  /* interrupts */
>  #define DE_MASTER_IRQ_CONTROL   (1 << 31)
>  #define DE_SPRITEB_FLIP_DONE    (1 << 29)
> -- 
> 2.21.0
>