[Intel-gfx] [PATCH 10/11] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink

[Navare, Manasi]

@Jani could you review this as well?

Manasi


On Thu, Oct 22, 2020 at 03:27:08PM -0700, Manasi Navare wrote:
> If VRR is enabled, the sink should ignore MSA parameters
> and regenerate incoming video stream without depending
> on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
> bit if VRR is enabled.
> Reset this bit on VRR disable.
> 
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Jani Nikula <jani.nikula at linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 25 ++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 565155af3fb9..195449dfec1e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3322,6 +3322,22 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
>  		return DP_TP_STATUS(encoder->port);
>  }
>  
> +static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
> +							  const struct intel_crtc_state *crtc_state,
> +							  bool enable)
> +{
> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> +	if (!crtc_state->vrr.enable)
> +		return;
> +
> +	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> +			       enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
> +		drm_dbg_kms(&i915->drm,
> +			    "Failed to set MSA_TIMING_PAR_IGNORE %s in the sink\n",
> +			    enable ? "enable" : "disable");
> +}
> +
>  static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
>  					const struct intel_crtc_state *crtc_state)
>  {
> @@ -3493,6 +3509,12 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  	 */
>  	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
>  
> +	/*
> +	 * Sink device should ignore MSA parameters and regenerate
> +	 * incoming video stream in case of VRR/Adaptive Sync
> +	 */
> +	intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, crtc_state, true);
> +
>  	/*
>  	 * 7.i Follow DisplayPort specification training sequence (see notes for
>  	 *     failure handling)
> @@ -4089,6 +4111,9 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state,
>  	/* Disable the decompression in DP Sink */
>  	intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
>  					      false);
> +	/* Disable Ignore_MSA bit in DP Sink */
> +	intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
> +						      false);
>  }
>  
>  static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
> -- 
> 2.19.1
>