[Intel-gfx] [PATCH 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7

[Chris Wilson]

Quoting Mika Kuoppala (2020-02-06 16:32:22)
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> 
> > Trust that the HW does the right thing after simply updating the
> > PD_DIR_BASE?
> 
> Bspec offers an invalidate before writing the base.
> 
> So, lets assume the DCLV write is superfluous as it will be
> the same.
> 
> Then the sequence would be TLB_INVLIDATE followed by
> PP_DIR_BASE (which will all pds)

I can recommend not doing the 
	*cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
first.
-Chris