[Intel-gfx] [PATCH 2/2] drm/i915: Move ringbuffer WAs to engine workaround list

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2020-01-29 23:59:00)
> Now that intel_engine_apply_workarounds is called on all gens, we can
> use the engine workaround lists for pre-gen8 workarounds as well to be
> consistent in the way we handle and dump the WAs.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>

If you go looking, you'll find plenty more gen2-7 w/a scattered about
the place.

> +static void
> +wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> +{
> +       wa_write_masked_or(wal, reg, val, _MASKED_BIT_DISABLE(val));
> +}
> +
>  static void
>  wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>  {
> @@ -1457,6 +1463,51 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>                             GEN8_L3SQCREG4,
>                             GEN8_LQSC_FLUSH_COHERENT_LINES);
>         }
> +
> +       if (IS_GEN(i915, 7))
> +               /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
> +               wa_masked_en(wal,
> +                            GFX_MODE_GEN7,
> +                            GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
> +
> +       if (IS_GEN_RANGE(i915, 6, 7))
> +               /*
> +                * We need to disable the AsyncFlip performance optimisations in
> +                * order to use MI_WAIT_FOR_EVENT within the CS. It should
> +                * already be programmed to '1' on all products.
> +                *
> +                * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
> +                */
> +               wa_masked_en(wal,
> +                            MI_MODE,
> +                            ASYNC_FLIP_PERF_DISABLE);
> +
> +       if (IS_GEN(i915, 6)) {
> +               /*
> +                * Required for the hardware to program scanline values for
> +                * waiting
> +                * WaEnableFlushTlbInvalidationMode:snb
> +                */
> +               wa_masked_en(wal,
> +                            GFX_MODE,
> +                            GFX_TLB_INVALIDATE_EXPLICIT);
> +
> +               /*
> +                * From the Sandybridge PRM, volume 1 part 3, page 24:
> +                * "If this bit is set, STCunit will have LRA as replacement
> +                *  policy. [...] This bit must be reset. LRA replacement
> +                *  policy is not supported."
> +                */
> +               wa_masked_dis(wal,
> +                             CACHE_MODE_0,
> +                             CM0_STC_EVICT_DISABLE_LRA_SNB);
> +       }
> +
> +       if (IS_GEN_RANGE(i915, 4, 6))
> +               /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> +               wa_masked_en(wal,
> +                            MI_MODE,
> +                            VS_TIMER_DISPATCH);
>  }

Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>

Let's hope this holds up in testing, now that we expose it to the tests!

>  static void
> @@ -1475,7 +1526,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  static void
>  engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  {
> -       if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
> +       if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
>                 return;
>  
>         if (engine->class == RENDER_CLASS)
> @@ -1488,7 +1539,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
>  {
>         struct i915_wa_list *wal = &engine->wa_list;
>  
> -       if (INTEL_GEN(engine->i915) < 8)
> +       if (INTEL_GEN(engine->i915) < 4)
>                 return;

Can we drop this yet? It's easy to overlook when extending the list of
w/a, so quite surprising.
-Chris