[Intel-gfx] [PATCH v6 6/7] drm/i915/dp: Register definition for DP compliance register

[Manna, Animesh]

On 19-03-2020 01:34, Manasi Navare wrote:
> On Wed, Mar 18, 2020 at 12:05:14PM +0530, Animesh Manna wrote:
>> DP_COMP_CTL and DP_COMP_PAT register used to program DP
>> compliance pattern.
>>
>> v1: Initial patch.
>> v2: used pipe instead of port in macro definition. [Manasi]
>> v3: used trans_offset for offset calculation. [Manasi]
>>
>> Reviewed-by: Manasi Navare <manasi.d.navare at intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna at intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 309cb7d96b35..8b6c9fbfe74b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9792,6 +9792,22 @@ enum skl_power_gate {
>>   #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
>>   #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>>   
>> +/* DDI DP Compliance Control */
>> +#define _DDI_DP_COMP_CTL_A			0x605F0
>> +#define DDI_DP_COMP_CTL(pipe)			_MMIO_TRANS2(pipe, _DDI_DP_COMP_CTL_A)
> Any reason why you couldnt use _MMIO_PIPE2 ?

As DP_COMP_CTL is part of transcoder register group, so I choose _MMIO_TRANS2 for calculation. Yes _MMIO_PIPE2 will also work as the offset difference between subsequent pipe is same (0x1000).
If the offset difference of subsequent transcoder register is different from the difference of subsequent pipe register we may have issue that time.

>
>> +#define   DDI_DP_COMP_CTL_ENABLE		(1 << 31)
>> +#define   DDI_DP_COMP_CTL_D10_2			(0 << 28)
>> +#define   DDI_DP_COMP_CTL_SCRAMBLED_0		(1 << 28)
>> +#define   DDI_DP_COMP_CTL_PRBS7			(2 << 28)
>> +#define   DDI_DP_COMP_CTL_CUSTOM80		(3 << 28)
>> +#define   DDI_DP_COMP_CTL_HBR2			(4 << 28)
>> +#define   DDI_DP_COMP_CTL_SCRAMBLED_1		(5 << 28)
>> +#define   DDI_DP_COMP_CTL_HBR2_RESET		(0xFC << 0)
>> +
>> +/* DDI DP Compliance Pattern */
>> +#define _DDI_DP_COMP_PAT_A			0x605F4
>> +#define DDI_DP_COMP_PAT(pipe, i)		_MMIO(_TRANS2(pipe, _DDI_DP_COMP_PAT_A) + (i) * 4)
> Why cant you use a simple _MMIO_PIPE2(pipe,  _DDI_DP_COMP_PAT_A) ?
> The offsets are same as the DP_COMP_CTL

Here extra parameter "i" needed for 80 bit custom pattern & as mentioned above DDI_DP_COMP_PAT is also part of transcoder register group,
so used _TRANS2 macro to calculate the offset then convert into mmio_reg.

Regards,
Animesh

>
> Manasi
>
>> +
>>   /* Sideband Interface (SBI) is programmed indirectly, via
>>    * SBI_ADDR, which contains the register offset; and SBI_DATA,
>>    * which contains the payload */
>> -- 
>> 2.24.0
>>