[Intel-gfx] [PATCH v3 3/5] drm/i915/dg2: Add Wa_16011777198

[Clint Taylor]

Correct,

Reviewed-by: Clint Taylor <Clinton.A.Taylor at intel.com>

-Clint



On 11/16/21 9:48 AM, Matt Roper wrote:
> Coarse power gating for render should not be enabled on some DG2
> steppings.
>
> Bspec: 52698
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++++++++++----
>   1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 43093dd2d0c9..c3155ee58689 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -117,10 +117,17 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>   			GEN6_RC_CTL_RC6_ENABLE |
>   			GEN6_RC_CTL_EI_MODE(1);
>   
> -	pg_enable =
> -		GEN9_RENDER_PG_ENABLE |
> -		GEN9_MEDIA_PG_ENABLE |
> -		GEN11_MEDIA_SAMPLER_PG_ENABLE;
> +	/* Wa_16011777198 - Render powergating must remain disabled */
> +	if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
> +	    IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
> +		pg_enable =
> +			GEN9_MEDIA_PG_ENABLE |
> +			GEN11_MEDIA_SAMPLER_PG_ENABLE;
> +	else
> +		pg_enable =
> +			GEN9_RENDER_PG_ENABLE |
> +			GEN9_MEDIA_PG_ENABLE |
> +			GEN11_MEDIA_SAMPLER_PG_ENABLE;
>   
>   	if (GRAPHICS_VER(gt->i915) >= 12) {
>   		for (i = 0; i < I915_MAX_VCS; i++)