[Intel-gfx] [PATCH v3 4/5] drm/i915/dg2: Add Wa_16013000631

[Clint Taylor]

Reviewed-by: Clint Taylor <Clinton.A.Taylor at intel.com>

-Clint


On 11/16/21 9:48 AM, Matt Roper wrote:
> From: Ramalingam C <ramalingam.c at intel.com>
>
> Invalidate IC cache through pipe control command as part of the ctx
> restore flow through indirect ctx pointer.
>
> v2:
>   - Move pipe control from xcs indirect context to the rcs indirect
>     context.  We'll eventually need this on the CCS engines too, but
>     support for those hasn't landed yet.
>
> Cc: Chris Wilson <chris.p.wilson at intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 56156cf18c41..b3489599e4de 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1167,6 +1167,11 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
>   	cs = gen12_emit_cmd_buf_wa(ce, cs);
>   	cs = gen12_emit_restore_scratch(ce, cs);
>   
> +	/* Wa_16013000631:dg2 */
> +	if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) ||
> +	    IS_DG2_G11(ce->engine->i915))
> +		cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0);
> +
>   	return cs;
>   }
>