[Intel-gfx] [PATCH v2] drm/i915: Add link rate and lane count to i915_display_info

[Navare, Manasi]

On Fri, Feb 05, 2021 at 11:09:36AM -0800, Khaled Almahallawy wrote:
> Link rate and lane count information are more easier and faster to check in i915_display_info
> than checking kernel logs for people not familiar with i915 in the following scenarios:
> * Debugging DP tunnel bandwidth usage in Thunderbolt driver.
> * In USB4 certification, it is a requirement to know which link rate used by
>   monitor to prove that DP tunnel handle up to HBR3
> * In PHY Compliance, when the connector propes are not mounted correctly,
>   some display lanes will not show up in the DP Oscilloscope and will fail CTS.
>   Just give the tester an easy way to identify where the problem is.
> 
> v2(Ville): Uniform style for '=' and use 'port clock' instead of 'link rate'

Yes this is really good, having this as part of display_info.
I am just wondering if this makes sense to be part of connector_info or crtc_info
What would be more readable and intuitive. But again since its part
of crtc_state, may be easier to be part of crtc_info.

Manasi


> 
> Cc: Imre Deak <imre.deak at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> CC: José Roberto de Souza <jose.souza at intel.com>
> Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index d62b18d5ecd8..cb088a0a26f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -990,9 +990,10 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>  			   yesno(crtc_state->hw.active),
>  			   DRM_MODE_ARG(&crtc_state->hw.adjusted_mode));
>  
> -		seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d\n",
> +		seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d, port clock=%d, lane count=%d\n",
>  			   crtc_state->pipe_src_w, crtc_state->pipe_src_h,
> -			   yesno(crtc_state->dither), crtc_state->pipe_bpp);
> +			   yesno(crtc_state->dither), crtc_state->pipe_bpp,
> +			   crtc_state->port_clock, crtc_state->lane_count);
>  
>  		intel_scaler_info(m, crtc);
>  	}
> -- 
> 2.25.1
> 
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