[Intel-gfx] [PATCH 5/5] drm/i915: Get proper min cdclk if vDSC enabled

[Lee, Shawn C]

On Tue, July 19, 2021, Vandita Kulkarni <vandita.kulkarni at intel.com> wrote:
>> 
>> VDSC engine can process only 1 pixel per Cd clock. In case VDSC is 
>> used and max slice count == 1, max supported pixel clock should be 100% of CD clock.
>> Then do min_cdclk and pixel clock comparison to get proper min cdclk.
>> 
>> Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
>> Cc: Jani Nikula <jani.nikula at linux.intel.com>
>> Cc: Vandita Kulkarni <vandita.kulkarni at intel.com>
>> Cc: Cooper Chiou <cooper.chiou at intel.com>
>> Cc: William Tseng <william.tseng at intel.com>
>> Signed-off-by: Lee Shawn C <shawn.c.lee at intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 71067a62264d..c33d574eb991 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2159,6 +2159,18 @@ int intel_crtc_compute_min_cdclk(const struct 
>> intel_crtc_state *crtc_state)
>>  /* Account for additional needs from the planes */  min_cdclk = 
>> max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>> 
>> +/*
>> + * VDSC engine can process only 1 pixel per Cd clock.
>> + * In case VDSC is used and max slice count == 1,
>> + * max supported pixel clock should be 100% of CD clock.
>> + * Then do min_cdclk and pixel clock comparison to get cdclk.
>> + */
>> +if (DISPLAY_VER(dev_priv) >= 11 &&
>
>I think you could just check for dsc enable and slice count ==1.
>

DP and eDP would apply the same thing if dsc enabled and sink's dsc slice count ==1.
Is that right?

>Also better to have a check if crtc_clock exceeds dev_priv->max_cdclk_freq in dsi_dsc compute_config as well.
>and return -EINVAL .
>
>-Vandita
>

We should have this checking in dsi_dsc_compute_config() just like DP driver did. What do you think?

	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
	    pipe_config->bigjoiner) {
		if (pipe_config->dsc.slice_count < 2) {
			drm_dbg_kms(&dev_priv->drm,
				    "Cannot split stream to use 2 VDSC instances\n");
			return -EINVAL;
		}

		pipe_config->dsc.dsc_split = true;
	}

Best regards,
Shawn

>> +    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
>> +    crtc_state->dsc.compression_enable &&
>> +    crtc_state->dsc.slice_count == 1)
>
>> +min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
>> +
>>  /*
>>   * HACK. Currently for TGL platforms we calculate
>>   * min_cdclk initially based on pixel_rate divided
>> --
>> 2.17.1
>
>