[Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx at lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits
> for blocks & lines
> 
> ADL-P further extends the bits in PLANE_WM that represent blocks and lines;
> we need to extend our masks accordingly.  Since these bits are reserved and
> MBZ on earlier platforms, it's safe to use the larger bitmask on all platforms.
> 
> Bspec: 50419
> Cc: Matt Atwood <matthew.s.atwood at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor at intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index cdb2f7b136a9..1d0cb423720e
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6439,8 +6439,8 @@ enum {
>  #define _PLANE_WM_TRANS_2_B	0x71368
>  #define   PLANE_WM_EN		(1 << 31)
>  #define   PLANE_WM_IGNORE_LINES	(1 << 30)
> -#define   PLANE_WM_LINES_MASK	REG_GENMASK(21, 14)
> -#define   PLANE_WM_BLOCKS_MASK	0x7ff /* skl+: 10 bits, icl+ 11 bits */
> +#define   PLANE_WM_LINES_MASK	REG_GENMASK(26, 14)
> +#define   PLANE_WM_BLOCKS_MASK	REG_GENMASK(11, 0)
> 
>  #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
> #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
> --
> 2.25.4
> 
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