[Intel-gfx] [PATCH 1/3] drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing

[Matthew Auld]

On Mon, 25 Apr 2022 at 16:22, Ramalingam C <ramalingam.c at intel.com> wrote:
>
> From: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>
>
> When bit 19 of MI_LOAD_REGISTER_IMM instruction opcode is set on tgl+
> devices, HW does not care about certain register address offsets, but
> instead check the following for valid address ranges on specific engines:
>         RCS && CCS: BITS(0 - 10)
>         BCS: BITS(0 - 11)
>         VECS && VCS: BITS(0 - 13)
> Also, tgl+ now support relative addressing for BCS engine - So, this
> patch fixes issue with live_gt_lrc selftest that is failing where there is
> mismatch between LRC register layout generated during init and HW
> default register offsets.
>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>
> cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
Reviewed-by: Matthew Auld <matthew.auld at intel.com>