[Intel-gfx] [PATCH v12 1/6] drm: Add arch arm64 for drm_clflush_virt_range

[Michael Cheng]

Hi Robin,

[ +arm64 maintainers for their awareness, which would have been a good 
thing to do from the start ]

  * Thanks for adding the arm64 maintainer and sorry I didn't rope them
    in sooner.

Why does i915 need to ensure the CPU's instruction cache is coherent 
with its data cache? Is it a self-modifying driver?

  * Also thanks for pointing this out. Initially I was using
    dcache_clean_inval_poc, which seem to be the equivalently to what
    x86 is doing for dcache flushing, but it was giving me build errors
    since its not on the global list of kernel symbols. And after
    revisiting the documentation for caches_clean_inval_pou, it won't
    fly for what we are trying to do. Moving forward, what would you (or
    someone in the ARM community) suggest we do? Could it be possible to
    export dcache_clean_inval_poc as a global symbol?

On 2022-02-25 10:24 a.m., Robin Murphy wrote:
> [ +arm64 maintainers for their awareness, which would have been a good 
> thing to do from the start ]
>
> On 2022-02-25 03:24, Michael Cheng wrote:
>> Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou
>> performs a flush by first performing a clean, follow by an invalidation
>> operation.
>>
>> v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
>>             dcache. Thanks Tvrtko for the suggestion.
>>
>> v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
>>
>> v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a
>>             symbol that could be use by other modules, thus use
>>             caches_clean_inval_pou instead. Also this version
>>                 removes include for cacheflush, since its already
>>             included base on architecture type.
>>
>> Signed-off-by: Michael Cheng <michael.cheng at intel.com>
>> Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
>> ---
>>   drivers/gpu/drm/drm_cache.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
>> index c3e6e615bf09..81c28714f930 100644
>> --- a/drivers/gpu/drm/drm_cache.c
>> +++ b/drivers/gpu/drm/drm_cache.c
>> @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long 
>> length)
>>         if (wbinvd_on_all_cpus())
>>           pr_err("Timed out waiting for cache flush\n");
>> +
>> +#elif defined(CONFIG_ARM64)
>> +    void *end = addr + length;
>> +    caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
>
> Why does i915 need to ensure the CPU's instruction cache is coherent 
> with its data cache? Is it a self-modifying driver?
>
> Robin.
>
> (Note that the above is somewhat of a loaded question, and I do 
> actually have half an idea of what you're trying to do here and why it 
> won't fly, but I'd like to at least assume you've read the 
> documentation of the function you decided was OK to use)
>
>> +
>>   #else
>>       WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
>>   #endif
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