[Intel-gfx] [PATCH 5/7] drm/i915/pcode: DGFX PCODE MBOX headers

[Anshuman Gupta]

DGFX uses similar PCODE MBOX interface as IGFX but
uses distinct COMMAND and PARAM set of bit fields.
Adding those headers Accordingly.

Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit at intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 321a08281a3f..ec2609fa233b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6735,6 +6735,9 @@
 
 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
 #define   GEN6_PCODE_READY			(1 << 31)
+#define   GEN6_PCODE_MB_PARAM2                  REG_GENMASK(23, 16)
+#define   GEN6_PCODE_MB_PARAM1                  REG_GENMASK(15, 8)
+#define   GEN6_PCODE_MB_COMMAND                 REG_GENMASK(7, 0)
 #define   GEN6_PCODE_ERROR_MASK			0xFF
 #define     GEN6_PCODE_SUCCESS			0x0
 #define     GEN6_PCODE_ILLEGAL_CMD		0x1
-- 
2.26.2