[Intel-gfx] [PATCH 6/7] drm/i915/dgfx: Setup VRAM SR with D3COLD
Anshuman Gupta
anshuman.gupta at intel.com
Wed May 18 13:07:15 UTC 2022
Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit, example PCI state.
Cc: Jani Nikula <jani.nikula at intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
---
drivers/gpu/drm/i915/i915_driver.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 7 +++++
drivers/gpu/drm/i915/i915_reg.h | 4 +++
drivers/gpu/drm/i915/intel_pcode.c | 25 +++++++++++++++++
drivers/gpu/drm/i915/intel_pcode.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 43 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.h | 2 ++
7 files changed, 84 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index ed6028fd442d..5a9d5529fc90 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -633,6 +633,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
if (ret)
goto err_msi;
+ intel_pm_vram_sr_setup(dev_priv);
+
/*
* Fill the dram structure to get the system dram info. This will be
* used for memory latency calculation.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 42463dc2979f..e15207e6a166 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -688,6 +688,13 @@ struct drm_i915_private {
u32 bxt_phy_grc;
u32 suspend_count;
+
+ struct {
+ /* lock to protect vram_sr flags */
+ struct mutex lock;
+ bool supported;
+ } vram_sr;
+
struct i915_suspend_saved_registers regfile;
struct vlv_s0ix_state *vlv_s0ix_state;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ec2609fa233b..50e6c7266f7a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6803,11 +6803,15 @@
#define DG1_PCODE_STATUS 0x7E
#define DG1_UNCORE_GET_INIT_STATUS 0x0
#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
+#define DG1_PCODE_D3_VRAM_SR 0x71
+#define DG1_ENABLE_SR 0x1
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
+#define VRAM_CAPABILITY _MMIO(0x138144)
+#define VRAM_SUPPORTED REG_BIT(0)
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index ac727546868e..43b2e7cfc458 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -225,3 +225,28 @@ int intel_pcode_init(struct drm_i915_private *i915)
return ret;
}
+
+/**
+ * intel_pcode_enable_vram_sr - Enable pcode vram_sr.
+ * @dev_priv: i915 device
+ *
+ * This function triggers the required pcode flow to enable vram_sr.
+ * This function stictly need to call from rpm handlers, as i915 is
+ * transitioning to rpm idle/suspend, it doesn't require to grab
+ * rpm wakeref.
+ */
+int intel_pcode_enable_vram_sr(struct drm_i915_private *i915)
+{
+ int ret = 0;
+
+ if (!HAS_LMEM_SR(i915))
+ return ret;
+
+ ret = snb_pcode_write(i915,
+ REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND,
+ DG1_PCODE_D3_VRAM_SR) |
+ REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1,
+ DG1_ENABLE_SR), 0); /* no data needed for this cmd */
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 0962a17fac48..3f695bd027a1 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -20,5 +20,6 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
int intel_pcode_init(struct drm_i915_private *i915);
+int intel_pcode_enable_vram_sr(struct drm_i915_private *i915);
#endif /* _INTEL_PCODE_H */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee0047fdc95d..6c14752f2dc8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8153,6 +8153,49 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
}
+void intel_pm_vram_sr_setup(struct drm_i915_private *i915)
+{
+ if (!HAS_LMEM_SR(i915))
+ return;
+
+ mutex_init(&i915->vram_sr.lock);
+
+ i915->vram_sr.supported = intel_uncore_read(&i915->uncore,
+ VRAM_CAPABILITY) & VRAM_SUPPORTED;
+ if (intel_opregion_vram_sr_required(i915))
+ i915->vram_sr.supported = i915->vram_sr.supported &&
+ intel_opregion_bios_supports_vram_sr(i915);
+}
+
+int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+ int ret = 0;
+
+ if (!HAS_LMEM_SR(i915))
+ return -EOPNOTSUPP;
+
+ mutex_lock(&i915->vram_sr.lock);
+ if (!i915->vram_sr.supported) {
+ drm_dbg(&i915->drm, "VRAM Self Refresh is not supported\n");
+ ret = -EOPNOTSUPP;
+ goto unlock;
+ }
+
+ drm_dbg(&i915->drm, "VRAM Self Refresh supported\n");
+ if (enable)
+ ret = intel_pcode_enable_vram_sr(i915);
+
+ if (ret)
+ goto unlock;
+
+ intel_opregion_vram_sr(i915, enable);
+
+unlock:
+ mutex_unlock(&i915->vram_sr.lock);
+
+ return ret;
+}
+
static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
{
struct intel_dbuf_state *dbuf_state;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 50604cf7398c..0da85d6b9ea7 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -31,6 +31,8 @@ int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
void intel_init_pm(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
void intel_pm_setup(struct drm_i915_private *dev_priv);
+void intel_pm_vram_sr_setup(struct drm_i915_private *i915);
+int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable);
void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
--
2.26.2
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