[Intel-gfx] [PATCH 2/8] drm/i915/mtl: Define MOCS and PAT tables for MTL

[Andi Shyti]

Hi Fei,

On Wed, Apr 19, 2023 at 02:12:13PM -0700, fei.yang at intel.com wrote:
> From: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep at intel.com>
> 
> On MTL, GT can no longer allocate on LLC - only the CPU can.
> This, along with addition of support for L4 cache calls for
> a MOCS/PAT table update.
> Also the PAT index registers are multicasted for primary GT,
> and there is an address jump from index 7 to 8. This patch
> makes sure that these registers are programmed in the proper
> way.
> 
> BSpec: 44509, 45101, 44235
> 
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep at intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty at intel.com>
> Signed-off-by: Nirmoy Das <nirmoy.das at intel.com>
> Signed-off-by: Fei Yang <fei.yang at intel.com>

I think nothing open left here.

Reviewed-by: Andi Shyti <andi.shyti at linux.intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda at intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das at intel.com>

Andi