[Intel-gfx] [PATCH 2/8] drm/i915/mtl: Define MOCS and PAT tables for MTL

[Yang, Fei]

> Hi Fei,
>
>> +#define MTL_PPGTT_PTE_PAT3  BIT_ULL(62)
>>  #define GEN12_PPGTT_PTE_LM  BIT_ULL(11)
>> +#define GEN12_PPGTT_PTE_PAT2        BIT_ULL(7)
>> +#define GEN12_PPGTT_PTE_NC  BIT_ULL(5)
>> +#define GEN12_PPGTT_PTE_PAT1        BIT_ULL(4)
>> +#define GEN12_PPGTT_PTE_PAT0        BIT_ULL(3)
>>
>> -#define GEN12_GGTT_PTE_LM   BIT_ULL(1)
>> +#define GEN12_GGTT_PTE_LM           BIT_ULL(1)
>> +#define MTL_GGTT_PTE_PAT0           BIT_ULL(52)
>> +#define MTL_GGTT_PTE_PAT1           BIT_ULL(53)
>> +#define GEN12_GGTT_PTE_ADDR_MASK    GENMASK_ULL(45, 12)
>> +#define MTL_GGTT_PTE_PAT_MASK               GENMASK_ULL(53, 52)
>>
>>  #define GEN12_PDE_64K BIT(6)
>>  #define GEN12_PTE_PS64 BIT(8)
>> @@ -147,6 +156,15 @@ typedef u64 gen8_pte_t;  #define GEN8_PDE_IPS_64K
>> BIT(11)
>>  #define GEN8_PDE_PS_2M   BIT(7)
>>
>> +#define MTL_PPAT_L4_CACHE_POLICY_MASK       REG_GENMASK(3, 2)
>> +#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
>> +#define MTL_PPAT_L4_3_UC    REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 3)
>> +#define MTL_PPAT_L4_1_WT    REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 1)
>> +#define MTL_PPAT_L4_0_WB    REG_FIELD_PREP(MTL_PPAT_L4_CACHE_POLICY_MASK, 0)
>> +#define MTL_3_COH_2W        REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 3)
>> +#define MTL_2_COH_1W        REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)
>> +#define MTL_0_COH_NON       REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 0)
>
> BTW, are all these defines needed? Not all of them look to be used.

Yes, these are all being used, not in this patch though, but in the next patch defining pte_encode functions.
I think the only one that might not be used is MTL_GGTT_PTE_PAT_MASK, because I ended up checking each bit instead of taking the PAT bits out and comparing against possible values.

-Fei

> Andi