[Intel-gfx] [PATCH] drm/i915/dsi: fix DSS CTL register offsets for TGL+

[Ville Syrjälä]

On Wed, Mar 01, 2023 at 05:38:39PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 01, 2023 at 05:14:09PM +0200, Jani Nikula wrote:
> > On TGL+ the DSS control registers are at different offsets, and there's
> > one per pipe. Fix the offsets to fix dual link DSI for TGL+.
> > 
> > There would be helpers for this in the DSC code, but just do the quick
> > fix now for DSI. Long term, we should probably move all the DSS handling
> > into intel_vdsc.c, so exporting the helpers seems counter-productive.
> 
> I'm not entirely happy with intel_vdsc.c since it handles
> both the hardware VDSC block (which includes DSS, and so
> also uncompressed joiner and MSO), and also some actual
> DSC calculations/etc. Might be nice to have a cleaner
> split of some sort.
> 
> That also reminds me that MSO+dsc/joiner is probably going
> to fail miserably given that neither side knows about the
> other and both poke the DSS registers.

I suppose MSO+joiner should just be rejected outright since 
the splitter seems to sit before the joiner in the path.
We'd need them to be the other way around.

But MSO+DSC does look plausible.

-- 
Ville Syrjälä
Intel